@@ -42,7 +42,7 @@ static aarch64_fbsd_nat_target the_aarch64_fbsd_nat_target;
static bool
getregs_supplies (struct gdbarch *gdbarch, int regnum)
{
- return (regnum >= AARCH64_X0_REGNUM && regnum <= AARCH64_CPSR_REGNUM);
+ return (regnum >= AARCH64_X0_REGNUM && regnum <= AARCH64_PSTATE_REGNUM);
}
/* Determine if PT_GETFPREGS fetches REGNUM. */
@@ -87,7 +87,7 @@ aarch64_fbsd_sigframe_init (const struct tramp_frame *self,
mcontext_addr + 31 * AARCH64_MCONTEXT_REG_SIZE);
trad_frame_set_reg_addr (this_cache, AARCH64_PC_REGNUM,
mcontext_addr + 32 * AARCH64_MCONTEXT_REG_SIZE);
- trad_frame_set_reg_addr (this_cache, AARCH64_CPSR_REGNUM,
+ trad_frame_set_reg_addr (this_cache, AARCH64_PSTATE_REGNUM,
mcontext_addr + 33 * AARCH64_MCONTEXT_REG_SIZE);
if (target_read_memory (mcontext_addr + AARCH64_MCONTEXT_FLAGS_OFFSET, buf,
@@ -135,7 +135,7 @@ static const struct regcache_map_entry aarch64_fbsd_gregmap[] =
{ 1, AARCH64_LR_REGNUM, 8 },
{ 1, AARCH64_SP_REGNUM, 8 },
{ 1, AARCH64_PC_REGNUM, 8 },
- { 1, AARCH64_CPSR_REGNUM, 4 },
+ { 1, AARCH64_PSTATE_REGNUM, 4 },
{ 0 }
};
@@ -230,7 +230,7 @@ fetch_gregs_from_thread (struct regcache *regcache)
{
int regno;
- for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
+ for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_PSTATE_REGNUM; regno++)
regcache->raw_supply (regno, ®s[regno - AARCH64_X0_REGNUM]);
}
}
@@ -267,7 +267,7 @@ store_gregs_to_thread (const struct regcache *regcache)
{
int regno;
- for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
+ for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_PSTATE_REGNUM; regno++)
if (REG_VALID == regcache->get_register_status (regno))
regcache->raw_collect (regno, ®s[regno - AARCH64_X0_REGNUM]);
}
@@ -193,7 +193,7 @@ static const struct regcache_map_entry aarch64_linux_gregmap[] =
{ 31, AARCH64_X0_REGNUM, 8 }, /* x0 ... x30 */
{ 1, AARCH64_SP_REGNUM, 8 },
{ 1, AARCH64_PC_REGNUM, 8 },
- { 1, AARCH64_CPSR_REGNUM, 8 },
+ { 1, AARCH64_PSTATE_REGNUM, 8 },
{ 0 }
};
@@ -950,7 +950,7 @@ aarch64_all_but_pc_registers_record (struct regcache *regcache)
if (record_full_arch_list_add_reg (regcache, i))
return -1;
- if (record_full_arch_list_add_reg (regcache, AARCH64_CPSR_REGNUM))
+ if (record_full_arch_list_add_reg (regcache, AARCH64_PSTATE_REGNUM))
return -1;
return 0;
@@ -995,8 +995,8 @@ aarch64_linux_syscall_record (struct regcache *regcache,
/* Record LR. */
if (record_full_arch_list_add_reg (regcache, AARCH64_LR_REGNUM))
return -1;
- /* Record CPSR. */
- if (record_full_arch_list_add_reg (regcache, AARCH64_CPSR_REGNUM))
+ /* Record PSTATE. */
+ if (record_full_arch_list_add_reg (regcache, AARCH64_PSTATE_REGNUM))
return -1;
return 0;
@@ -137,7 +137,7 @@ static const char *const aarch64_r_register_names[] =
"x20", "x21", "x22", "x23",
"x24", "x25", "x26", "x27",
"x28", "x29", "x30", "sp",
- "pc", "cpsr"
+ "pc", "pstate"
};
/* The FP/SIMD 'V' registers. */
@@ -3268,7 +3268,7 @@ aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
record_buf[0] = reg_rd;
aarch64_insn_r->reg_rec_count = 1;
if (setflags)
- record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
+ record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PSTATE_REGNUM;
}
else
{
@@ -3287,7 +3287,7 @@ aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
aarch64_insn_r->reg_rec_count = 1;
if (bit (aarch64_insn_r->aarch64_insn, 29))
{
- record_buf[1] = AARCH64_CPSR_REGNUM;
+ record_buf[1] = AARCH64_PSTATE_REGNUM;
aarch64_insn_r->reg_rec_count = 2;
}
}
@@ -3295,7 +3295,7 @@ aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
{
/* Conditional compare (register) and conditional compare
(immediate) instructions. */
- record_buf[0] = AARCH64_CPSR_REGNUM;
+ record_buf[0] = AARCH64_PSTATE_REGNUM;
aarch64_insn_r->reg_rec_count = 1;
}
else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
@@ -3342,7 +3342,7 @@ aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
record_buf[0] = reg_rd;
aarch64_insn_r->reg_rec_count = 1;
if (setflags)
- record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
+ record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PSTATE_REGNUM;
}
else if (insn_bits24_27 == 0x02 && !insn_bit23)
{
@@ -3351,7 +3351,7 @@ aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
record_buf[0] = reg_rd;
aarch64_insn_r->reg_rec_count = 1;
if (setflags)
- record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
+ record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PSTATE_REGNUM;
}
else
return AARCH64_RECORD_UNKNOWN;
@@ -3407,10 +3407,10 @@ aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
record_buf[0] = reg_rt;
aarch64_insn_r->reg_rec_count = 1;
}
- /* Record cpsr for hint and msr(immediate) instructions. */
+ /* Record pstate for hint and msr(immediate) instructions. */
else if (reg_crn == 0x02 || reg_crn == 0x04)
{
- record_buf[0] = AARCH64_CPSR_REGNUM;
+ record_buf[0] = AARCH64_PSTATE_REGNUM;
aarch64_insn_r->reg_rec_count = 1;
}
}
@@ -3937,7 +3937,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
if (record_debug)
debug_printf ("FP - conditional compare");
- record_buf[0] = AARCH64_CPSR_REGNUM;
+ record_buf[0] = AARCH64_PSTATE_REGNUM;
}
/* Floating point - data processing (2-source) and
conditional select instructions. */
@@ -3963,7 +3963,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
{
if (record_debug)
debug_printf ("FP - immediate");
- record_buf[0] = AARCH64_CPSR_REGNUM;
+ record_buf[0] = AARCH64_PSTATE_REGNUM;
}
/* Floating point - integer conversions instructions. */
else if (insn_bits12_15 == 0x00)
@@ -4160,9 +4160,9 @@ aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
/* Record registers. */
record_full_arch_list_add_reg (aarch64_record.regcache,
AARCH64_PC_REGNUM);
- /* Always record register CPSR. */
+ /* Always record register pstate. */
record_full_arch_list_add_reg (aarch64_record.regcache,
- AARCH64_CPSR_REGNUM);
+ AARCH64_PSTATE_REGNUM);
if (aarch64_record.aarch64_regs)
for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
if (record_full_arch_list_add_reg (aarch64_record.regcache,
@@ -38,7 +38,7 @@ enum aarch64_regnum
AARCH64_LR_REGNUM = AARCH64_X0_REGNUM + 30, /* Return address. */
AARCH64_SP_REGNUM, /* Stack pointer. */
AARCH64_PC_REGNUM, /* Program counter. */
- AARCH64_CPSR_REGNUM, /* Current Program Status Register. */
+ AARCH64_PSTATE_REGNUM, /* Process state. */
AARCH64_V0_REGNUM, /* First fp/vec register. */
AARCH64_V31_REGNUM = AARCH64_V0_REGNUM + 31, /* Last fp/vec register. */
AARCH64_SVE_Z0_REGNUM = AARCH64_V0_REGNUM, /* First SVE Z register. */
@@ -10,7 +10,7 @@ create_feature_aarch64_core (struct target_desc *result, long regnum)
feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.core");
tdesc_type_with_fields *type_with_fields;
- type_with_fields = tdesc_create_flags (feature, "cpsr_flags", 4);
+ type_with_fields = tdesc_create_flags (feature, "pstate_flags", 4);
tdesc_add_flag (type_with_fields, 0, "SP");
tdesc_add_flag (type_with_fields, 1, "");
tdesc_add_bitfield (type_with_fields, "EL", 2, 3);
@@ -60,6 +60,6 @@ create_feature_aarch64_core (struct target_desc *result, long regnum)
tdesc_create_reg (feature, "x30", regnum++, 1, NULL, 64, "int");
tdesc_create_reg (feature, "sp", regnum++, 1, NULL, 64, "data_ptr");
tdesc_create_reg (feature, "pc", regnum++, 1, NULL, 64, "code_ptr");
- tdesc_create_reg (feature, "cpsr", regnum++, 1, NULL, 32, "cpsr_flags");
+ tdesc_create_reg (feature, "pstate", regnum++, 1, NULL, 32, "pstate_flags");
return regnum;
}
@@ -43,7 +43,7 @@
<reg name="pc" bitsize="64" type="code_ptr"/>
- <flags id="cpsr_flags" size="4">
+ <flags id="pstate_flags" size="4">
<field name="SP" start="0" end="0"/>
<field name="" start="1" end="1"/>
<field name="EL" start="2" end="3"/>
@@ -62,6 +62,6 @@
<field name="Z" start="30" end="30"/>
<field name="N" start="31" end="31"/>
</flags>
- <reg name="cpsr" bitsize="32" type="cpsr_flags"/>
+ <reg name="pstate" bitsize="32" type="pstate_flags"/>
</feature>
@@ -32,7 +32,7 @@
#define FT_CR_FPCR 0
#define FT_CR_FPSR 1
-#define FT_CR_CPSR 2
+#define FT_CR_PSTATE 2
#define FT_CR_PC 3
#define FT_CR_SP 4
#define FT_CR_X0 5
@@ -81,7 +81,7 @@ static const int aarch64_ft_collect_regmap[] = {
FT_CR_GPR (30),
FT_CR_SP,
FT_CR_PC,
- FT_CR_CPSR,
+ FT_CR_PSTATE,
FT_CR_FPR (0),
FT_CR_FPR (1),
FT_CR_FPR (2),
@@ -110,7 +110,7 @@ aarch64_fill_gregset (struct regcache *regcache, void *buf)
collect_register (regcache, AARCH64_X0_REGNUM + i, ®set->regs[i]);
collect_register (regcache, AARCH64_SP_REGNUM, ®set->sp);
collect_register (regcache, AARCH64_PC_REGNUM, ®set->pc);
- collect_register (regcache, AARCH64_CPSR_REGNUM, ®set->pstate);
+ collect_register (regcache, AARCH64_PSTATE_REGNUM, ®set->pstate);
}
static void
@@ -123,7 +123,7 @@ aarch64_store_gregset (struct regcache *regcache, const void *buf)
supply_register (regcache, AARCH64_X0_REGNUM + i, ®set->regs[i]);
supply_register (regcache, AARCH64_SP_REGNUM, ®set->sp);
supply_register (regcache, AARCH64_PC_REGNUM, ®set->pc);
- supply_register (regcache, AARCH64_CPSR_REGNUM, ®set->pstate);
+ supply_register (regcache, AARCH64_PSTATE_REGNUM, ®set->pstate);
}
static void
@@ -796,8 +796,8 @@ postindex_memory_operand (int32_t index)
/* System control registers. These special registers can be written and
read with the MRS and MSR instructions.
- - NZCV: Condition flags. GDB refers to this register under the CPSR
- name.
+ - NZCV: Condition flags. GDB refers to this register under the PSTATE
+ name.
- FPSR: Floating-point status register.
- FPCR: Floating-point control registers.
- TPIDR_EL0: Software thread ID register. */
@@ -1890,12 +1890,12 @@ aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint,
to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
has to be 16 bytes aligned anyway.
- Note that the CPSR register does not exist on AArch64. Instead we
+ Note that the PSTATE register does not exist on AArch64. Instead we
can access system bits describing the process state with the
MRS/MSR instructions, namely the condition flags. We save them as
- if they are part of a CPSR register because that's how GDB
+ if they are part of a PSTATE register because that's how GDB
interprets these system bits. At the moment, only the condition
- flags are saved in CPSR (NZCV).
+ flags are saved in PSTATE (NZCV).
Stack layout, each cell is 16 bytes (descending):
@@ -1914,7 +1914,7 @@ aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint,
*------------- Special purpose registers. -------------*
| SP |
| PC |
- | CPSR (NZCV) | 5 cells
+ | PSTATE (NZCV) | 5 cells
| FPSR |
| FPCR | <- SP + 16
*------------- collecting_t object --------------------*
@@ -1982,7 +1982,7 @@ aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint,
p += emit_mov_addr (p, x3, tpaddr);
p += emit_str (p, x3, sp, offset_memory_operand (3 * 16));
- /* Save CPSR (NZCV), FPSR and FPCR:
+ /* Save PSTATE (NZCV), FPSR and FPCR:
MRS x2, nzcv
MRS x1, fpsr
@@ -2121,7 +2121,7 @@ aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint,
*/
p += emit_add (p, sp, sp, immediate_operand (16));
- /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
+ /* Restore PSTATE (NZCV), FPSR and FPCR. And free all special purpose
registers from the stack.
LDR x2, [sp, #(2 * 16)]
@@ -37,7 +37,7 @@ expedite:x29,sp,pc
64:x30
64:sp
64:pc
-32:cpsr
+32:pstate
128:v0
128:v1
128:v2
@@ -211,9 +211,9 @@ aarch64_save_LR (sim_cpu *cpu)
}
static const char *
-decode_cpsr (FlagMask flags)
+decode_pstate (FlagMask flags)
{
- switch (flags & CPSR_ALL_FLAGS)
+ switch (flags & PSTATE_ALL_FLAGS)
{
default:
case 0: return "----";
@@ -235,87 +235,87 @@ decode_cpsr (FlagMask flags)
}
}
-/* Retrieve the CPSR register as an int. */
+/* Retrieve the PSTATE register as an int. */
uint32_t
-aarch64_get_CPSR (sim_cpu *cpu)
+aarch64_get_PSTATE (sim_cpu *cpu)
{
- return cpu->CPSR;
+ return cpu->PSTATE;
}
-/* Set the CPSR register as an int. */
+/* Set the PSTATE register as an int. */
void
-aarch64_set_CPSR (sim_cpu *cpu, uint32_t new_flags)
+aarch64_set_PSTATE (sim_cpu *cpu, uint32_t new_flags)
{
if (TRACE_REGISTER_P (cpu))
{
- if (cpu->CPSR != new_flags)
+ if (cpu->PSTATE != new_flags)
TRACE_REGISTER (cpu,
- "CPSR changes from %s to %s",
- decode_cpsr (cpu->CPSR), decode_cpsr (new_flags));
+ "PSTATE changes from %s to %s",
+ decode_pstate (cpu->PSTATE), decode_pstate (new_flags));
else
TRACE_REGISTER (cpu,
- "CPSR stays at %s", decode_cpsr (cpu->CPSR));
+ "PSTATE stays at %s", decode_pstate (cpu->PSTATE));
}
- cpu->CPSR = new_flags & CPSR_ALL_FLAGS;
+ cpu->PSTATE = new_flags & PSTATE_ALL_FLAGS;
}
-/* Read a specific subset of the CPSR as a bit pattern. */
+/* Read a specific subset of the PSTATE as a bit pattern. */
uint32_t
-aarch64_get_CPSR_bits (sim_cpu *cpu, FlagMask mask)
+aarch64_get_PSTATE_bits (sim_cpu *cpu, FlagMask mask)
{
- return cpu->CPSR & mask;
+ return cpu->PSTATE & mask;
}
-/* Assign a specific subset of the CPSR as a bit pattern. */
+/* Assign a specific subset of the PSTATE as a bit pattern. */
void
-aarch64_set_CPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value)
+aarch64_set_PSTATE_bits (sim_cpu *cpu, uint32_t mask, uint32_t value)
{
- uint32_t old_flags = cpu->CPSR;
+ uint32_t old_flags = cpu->PSTATE;
- mask &= CPSR_ALL_FLAGS;
- cpu->CPSR &= ~ mask;
- cpu->CPSR |= (value & mask);
+ mask &= PSTATE_ALL_FLAGS;
+ cpu->PSTATE &= ~ mask;
+ cpu->PSTATE |= (value & mask);
- if (old_flags != cpu->CPSR)
+ if (old_flags != cpu->PSTATE)
TRACE_REGISTER (cpu,
- "CPSR changes from %s to %s",
- decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
+ "PSTATE changes from %s to %s",
+ decode_pstate (old_flags), decode_pstate (cpu->PSTATE));
}
-/* Test the value of a single CPSR returned as non-zero or zero. */
+/* Test the value of a single PSTATE returned as non-zero or zero. */
uint32_t
-aarch64_test_CPSR_bit (sim_cpu *cpu, FlagMask bit)
+aarch64_test_PSTATE_bit (sim_cpu *cpu, FlagMask bit)
{
- return cpu->CPSR & bit;
+ return cpu->PSTATE & bit;
}
-/* Set a single flag in the CPSR. */
+/* Set a single flag in the PSTATE. */
void
-aarch64_set_CPSR_bit (sim_cpu *cpu, FlagMask bit)
+aarch64_set_PSTATE_bit (sim_cpu *cpu, FlagMask bit)
{
- uint32_t old_flags = cpu->CPSR;
+ uint32_t old_flags = cpu->PSTATE;
- cpu->CPSR |= (bit & CPSR_ALL_FLAGS);
+ cpu->PSTATE |= (bit & PSTATE_ALL_FLAGS);
- if (old_flags != cpu->CPSR)
+ if (old_flags != cpu->PSTATE)
TRACE_REGISTER (cpu,
- "CPSR changes from %s to %s",
- decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
+ "PSTATE changes from %s to %s",
+ decode_pstate (old_flags), decode_pstate (cpu->PSTATE));
}
-/* Clear a single flag in the CPSR. */
+/* Clear a single flag in the PSTATE. */
void
-aarch64_clear_CPSR_bit (sim_cpu *cpu, FlagMask bit)
+aarch64_clear_PSTATE_bit (sim_cpu *cpu, FlagMask bit)
{
- uint32_t old_flags = cpu->CPSR;
+ uint32_t old_flags = cpu->PSTATE;
- cpu->CPSR &= ~(bit & CPSR_ALL_FLAGS);
+ cpu->PSTATE &= ~(bit & PSTATE_ALL_FLAGS);
- if (old_flags != cpu->CPSR)
+ if (old_flags != cpu->PSTATE)
TRACE_REGISTER (cpu,
- "CPSR changes from %s to %s",
- decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
+ "PSTATE changes from %s to %s",
+ decode_pstate (old_flags), decode_pstate (cpu->PSTATE));
}
float
@@ -217,7 +217,7 @@ typedef enum FlagMask
N = 1 << N_IDX
} FlagMask;
-#define CPSR_ALL_FLAGS (V | C | Z | N)
+#define PSTATE_ALL_FLAGS (V | C | Z | N)
typedef uint32_t FlagsRegister;
@@ -306,13 +306,13 @@ extern void aarch64_save_LR (sim_cpu *);
#define aarch64_get_instr(cpu) ((cpu)->instr)
/* Flag register accessors. */
-extern uint32_t aarch64_get_CPSR (sim_cpu *);
-extern void aarch64_set_CPSR (sim_cpu *, uint32_t);
-extern uint32_t aarch64_get_CPSR_bits (sim_cpu *, uint32_t);
-extern void aarch64_set_CPSR_bits (sim_cpu *, uint32_t, uint32_t);
-extern uint32_t aarch64_test_CPSR_bit (sim_cpu *, FlagMask);
-extern void aarch64_set_CPSR_bit (sim_cpu *, FlagMask);
-extern void aarch64_clear_CPSR_bit (sim_cpu *, FlagMask);
+extern uint32_t aarch64_get_PSTATE (sim_cpu *);
+extern void aarch64_set_PSTATE (sim_cpu *, uint32_t);
+extern uint32_t aarch64_get_PSTATE_bits (sim_cpu *, uint32_t);
+extern void aarch64_set_PSTATE_bits (sim_cpu *, uint32_t, uint32_t);
+extern uint32_t aarch64_test_PSTATE_bit (sim_cpu *, FlagMask);
+extern void aarch64_set_PSTATE_bit (sim_cpu *, FlagMask);
+extern void aarch64_clear_PSTATE_bit (sim_cpu *, FlagMask);
extern void aarch64_set_FPSR (sim_cpu *, uint32_t);
extern uint32_t aarch64_get_FPSR (sim_cpu *);
@@ -191,7 +191,7 @@ check_regno (int regno)
static size_t
reg_size (int regno)
{
- if (regno == AARCH64_CPSR_REGNO || regno == AARCH64_FPSR_REGNO)
+ if (regno == AARCH64_PSTATE_REGNO || regno == AARCH64_FPSR_REGNO)
return 32;
return 64;
}
@@ -224,8 +224,8 @@ aarch64_reg_get (SIM_CPU *cpu, int regno, unsigned char *buf, int length)
val = aarch64_get_PC (cpu);
break;
- case AARCH64_CPSR_REGNO:
- val = aarch64_get_CPSR (cpu);
+ case AARCH64_PSTATE_REGNO:
+ val = aarch64_get_PSTATE (cpu);
break;
case AARCH64_FPSR_REGNO:
@@ -274,8 +274,8 @@ aarch64_reg_set (SIM_CPU *cpu, int regno, unsigned char *buf, int length)
aarch64_update_PC (cpu);
break;
- case AARCH64_CPSR_REGNO:
- aarch64_set_CPSR (cpu, val);
+ case AARCH64_PSTATE_REGNO:
+ aarch64_set_PSTATE (cpu, val);
break;
case AARCH64_FPSR_REGNO:
@@ -36,7 +36,7 @@ struct _sim_cpu
FRegister fr[32];
uint64_t pc;
- uint32_t CPSR;
+ uint32_t PSTATE;
uint32_t FPSR; /* Floating point Status register. */
uint32_t FPCR; /* Floating point Control register. */
@@ -50,14 +50,14 @@ struct _sim_cpu
typedef enum
{
- AARCH64_MIN_GR = 0,
- AARCH64_MAX_GR = 31,
- AARCH64_MIN_FR = 32,
- AARCH64_MAX_FR = 63,
- AARCH64_PC_REGNO = 64,
- AARCH64_CPSR_REGNO = 65,
- AARCH64_FPSR_REGNO = 66,
- AARCH64_MAX_REGNO = 67
+ AARCH64_MIN_GR = 0,
+ AARCH64_MAX_GR = 31,
+ AARCH64_MIN_FR = 32,
+ AARCH64_MAX_FR = 63,
+ AARCH64_PC_REGNO = 64,
+ AARCH64_PSTATE_REGNO = 65,
+ AARCH64_FPSR_REGNO = 66,
+ AARCH64_MAX_REGNO = 67
} aarch64_regno;
/* The simulator state structure used to hold all global variables. */
@@ -35,7 +35,7 @@
#define NO_SP 0
#define SP_OK 1
-#define TST(_flag) (aarch64_test_CPSR_bit (cpu, _flag))
+#define TST(_flag) (aarch64_test_PSTATE_bit (cpu, _flag))
#define IS_SET(_X) (TST (( _X )) ? 1 : 0)
#define IS_CLEAR(_X) (TST (( _X )) ? 0 : 1)
@@ -1656,7 +1656,7 @@ set_flags_for_add32 (sim_cpu *cpu, int32_t value1, int32_t value2)
if (sresult != result)
flags |= V;
- aarch64_set_CPSR (cpu, flags);
+ aarch64_set_PSTATE (cpu, flags);
}
#define NEG(a) (((a) & signbit) == signbit)
@@ -1684,7 +1684,7 @@ set_flags_for_add64 (sim_cpu *cpu, uint64_t value1, uint64_t value2)
|| (POS (value1) && POS (value2) && NEG (result)))
flags |= V;
- aarch64_set_CPSR (cpu, flags);
+ aarch64_set_PSTATE (cpu, flags);
}
static void
@@ -1709,7 +1709,7 @@ set_flags_for_sub32 (sim_cpu *cpu, uint32_t value1, uint32_t value2)
|| (POS (value1) && NEG (value2) && NEG (result)))
flags |= V;
- aarch64_set_CPSR (cpu, flags);
+ aarch64_set_PSTATE (cpu, flags);
}
static void
@@ -1734,7 +1734,7 @@ set_flags_for_sub64 (sim_cpu *cpu, uint64_t value1, uint64_t value2)
|| (POS (value1) && NEG (value2) && NEG (result)))
flags |= V;
- aarch64_set_CPSR (cpu, flags);
+ aarch64_set_PSTATE (cpu, flags);
}
static void
@@ -1752,7 +1752,7 @@ set_flags_for_binop32 (sim_cpu *cpu, uint32_t result)
else
flags &= ~ N;
- aarch64_set_CPSR (cpu, flags);
+ aarch64_set_PSTATE (cpu, flags);
}
static void
@@ -1770,7 +1770,7 @@ set_flags_for_binop64 (sim_cpu *cpu, uint64_t result)
else
flags &= ~ N;
- aarch64_set_CPSR (cpu, flags);
+ aarch64_set_PSTATE (cpu, flags);
}
/* 32 bit add immediate set flags. */
@@ -2550,7 +2550,7 @@ CondCompare (sim_cpu *cpu) /* aka: ccmp and ccmn */
instr[10] = 0
instr[9,5] = Rn
instr[4] = 0
- instr[3,0] = value for CPSR bits if the comparison does not take place. */
+ instr[3,0] = value for PSTATE bits if the comparison does not take place. */
signed int negate;
unsigned rm;
unsigned rn;
@@ -2562,7 +2562,7 @@ CondCompare (sim_cpu *cpu) /* aka: ccmp and ccmn */
TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
if (! testConditionCode (cpu, INSTR (15, 12)))
{
- aarch64_set_CPSR (cpu, INSTR (3, 0));
+ aarch64_set_PSTATE (cpu, INSTR (3, 0));
return;
}
@@ -7293,7 +7293,7 @@ dexSimpleFPCondCompare (sim_cpu *cpu)
TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
if (! testConditionCode (cpu, INSTR (15, 12)))
{
- aarch64_set_CPSR (cpu, INSTR (3, 0));
+ aarch64_set_PSTATE (cpu, INSTR (3, 0));
return;
}
@@ -7305,11 +7305,11 @@ dexSimpleFPCondCompare (sim_cpu *cpu)
/* FIXME: Check for NaNs. */
if (val1 == val2)
- aarch64_set_CPSR (cpu, (Z | C));
+ aarch64_set_PSTATE (cpu, (Z | C));
else if (val1 < val2)
- aarch64_set_CPSR (cpu, N);
+ aarch64_set_PSTATE (cpu, N);
else /* val1 > val2 */
- aarch64_set_CPSR (cpu, C);
+ aarch64_set_PSTATE (cpu, C);
}
else
{
@@ -7319,11 +7319,11 @@ dexSimpleFPCondCompare (sim_cpu *cpu)
/* FIXME: Check for NaNs. */
if (val1 == val2)
- aarch64_set_CPSR (cpu, (Z | C));
+ aarch64_set_PSTATE (cpu, (Z | C));
else if (val1 < val2)
- aarch64_set_CPSR (cpu, N);
+ aarch64_set_PSTATE (cpu, N);
else /* val1 > val2 */
- aarch64_set_CPSR (cpu, C);
+ aarch64_set_PSTATE (cpu, C);
}
}
@@ -8655,7 +8655,7 @@ set_flags_for_float_compare (sim_cpu *cpu, float fvalue1, float fvalue2)
flags = C;
}
- aarch64_set_CPSR (cpu, flags);
+ aarch64_set_PSTATE (cpu, flags);
}
static void
@@ -8741,7 +8741,7 @@ set_flags_for_double_compare (sim_cpu *cpu, double dval1, double dval2)
flags = C;
}
- aarch64_set_CPSR (cpu, flags);
+ aarch64_set_PSTATE (cpu, flags);
}
/* Double compare -- Invalid Operation exception only on signaling NaNs. */
@@ -14003,7 +14003,7 @@ system_get (sim_cpu *cpu, unsigned op0, unsigned op1, unsigned crn,
return aarch64_get_FPSR (cpu);
else if (op1 == 3 && crm == 2 && op2 == 0)
- return aarch64_get_CPSR (cpu);
+ return aarch64_get_PSTATE (cpu);
HALT_NYI;
}
@@ -14019,7 +14019,7 @@ system_set (sim_cpu *cpu, unsigned op0, unsigned op1, unsigned crn,
aarch64_set_FPSR (cpu, val);
else if (op1 == 3 && crm == 2 && op2 == 0)
- aarch64_set_CPSR (cpu, val);
+ aarch64_set_PSTATE (cpu, val);
else
HALT_NYI;