From patchwork Wed Jul 4 00:13:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 28217 Received: (qmail 15945 invoked by alias); 4 Jul 2018 00:14:10 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 15931 invoked by uid 89); 4 Jul 2018 00:14:09 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:1434, HX-Received:sk:c8-v6mr, riscvtdepc, riscv-tdep.c X-HELO: mail-pl0-f67.google.com Received: from mail-pl0-f67.google.com (HELO mail-pl0-f67.google.com) (209.85.160.67) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 04 Jul 2018 00:14:07 +0000 Received: by mail-pl0-f67.google.com with SMTP id 31-v6so1773632plc.4 for ; Tue, 03 Jul 2018 17:14:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=bKxvYK+uWHq6Q/c48f+NtrB2aRLCl+gCwp9ZZxL+GGg=; b=bFsMwk3GBxGdw66Ufd3S1iXoXI42G05LjI3KBederskCUzlJn07Up2FfzOXR8Kvk9w xm2fbLaCeTxtoCktgy3YHPgLLsxlYxINszlta/ioaCWHF91getd0MrH2A+9o1N5NCtQT nvlGdo2pmZb13c8bQ/e65fTQC40jjD76WcSjZR0xQPkViP347e8n0PWb56tDfstkT4KZ 7FRztcSzkhwwB4Rsog/TTNTvouM/HcDiRrHE6ngfwjzwfaX4R6N4vSv7Lv72YZ37ZK8z 7Z8+sHs7tMl++d8smMLBKX4cbkW8Xgm9if6eweTuk0tifXM+hIwiDnuL/hFIym6TF6EA ngvQ== Return-Path: Received: from rohan.internal.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id r77-v6sm4414766pfr.117.2018.07.03.17.14.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 03 Jul 2018 17:14:05 -0700 (PDT) From: Jim Wilson To: gdb-patches@sourceware.org Cc: andrew.burgess@embecosm.com, Jim Wilson Subject: [PATCH] RISC-V: Correct legacy misa register number. Date: Tue, 3 Jul 2018 17:13:34 -0700 Message-Id: <20180704001334.27460-1-jimw@sifive.com> The main purpose of this patch is to fix the legacy misa register number, which is missing the +65 added to all of the other CSRs. This also changes DECLARE_CSR to use RISCV_FIRST_CSR_REGNUM instead of RISCV_LAST_FP_REGNUM+1 to be consistent with riscv-tdep.c. I don't have access to legacy hardware that I can test the misa number change with, but it has been tested on a riscv64-linux system using patched gdb and patched kernel, since it isn't usable otherwise. Jim gdb/ * riscv-tdep.h (DECLARE_CSR): Use RISCV_FIRST_CSR_REGNUM instead of RISCV_LAST_FP_REGNUM + 1. (RSICV_CSR_LEGACY_MISA_REGNUM): Add RISCV_FIRST_CSR_REGNUM. --- gdb/riscv-tdep.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h index ab5e278759..4fc05976ba 100644 --- a/gdb/riscv-tdep.h +++ b/gdb/riscv-tdep.h @@ -39,11 +39,11 @@ enum RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */ RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */ -#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_LAST_FP_REGNUM + 1 + num, +#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num, #include "opcode/riscv-opc.h" #undef DECLARE_CSR RISCV_LAST_CSR_REGNUM = 4160, - RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10, + RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM, RISCV_PRIV_REGNUM = 4161,