From patchwork Mon Mar 12 03:09:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Marchi X-Patchwork-Id: 26282 Received: (qmail 69690 invoked by alias); 12 Mar 2018 03:09:57 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 69679 invoked by uid 89); 12 Mar 2018 03:09:56 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy=H*RU:sk:barracu, HX-HELO:sk:barracu, Hx-spam-relays-external:sk:barracu, H*r:sk:barracu X-HELO: barracuda.ebox.ca Received: from barracuda.ebox.ca (HELO barracuda.ebox.ca) (96.127.255.19) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 12 Mar 2018 03:09:54 +0000 X-ASG-Debug-ID: 1520824183-0c856e618939f120001-fS2M51 Received: from smtp.ebox.ca (smtp.electronicbox.net [96.127.255.82]) by barracuda.ebox.ca with ESMTP id qGMI8BJPGvgyKE4G (version=TLSv1 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 11 Mar 2018 23:09:43 -0400 (EDT) X-Barracuda-Envelope-From: simon.marchi@polymtl.ca X-Barracuda-RBL-Trusted-Forwarder: 96.127.255.82 Received: from simark.lan (192-222-251-162.qc.cable.ebox.net [192.222.251.162]) by smtp.ebox.ca (Postfix) with ESMTP id AB2A0441B21; Sun, 11 Mar 2018 23:09:43 -0400 (EDT) From: Simon Marchi X-Barracuda-Effective-Source-IP: 192-222-251-162.qc.cable.ebox.net[192.222.251.162] X-Barracuda-Apparent-Source-IP: 192.222.251.162 X-Barracuda-RBL-IP: 192.222.251.162 To: gdb-patches@sourceware.org Cc: Simon Marchi Subject: [PATCH] Make arm_record_test work on big-endian machines Date: Sun, 11 Mar 2018 23:09:43 -0400 X-ASG-Orig-Subj: [PATCH] Make arm_record_test work on big-endian machines Message-Id: <20180312030943.32669-1-simon.marchi@polymtl.ca> X-Barracuda-Connect: smtp.electronicbox.net[96.127.255.82] X-Barracuda-Start-Time: 1520824183 X-Barracuda-Encrypted: DHE-RSA-AES256-SHA X-Barracuda-URL: https://96.127.255.19:443/cgi-mod/mark.cgi X-Barracuda-Scan-Msg-Size: 5268 X-Barracuda-BRTS-Status: 1 X-Barracuda-Spam-Score: 0.00 X-Barracuda-Spam-Status: No, SCORE=0.00 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=8.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.48846 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- X-IsSubscribed: yes While running selftests on a big-endian PPC, I noticed arm_record_test failed a test. The reason is that the gdbarch_find_by_info call is done with BFD_ENDIAN_UNKNOWN byte order in the info structure. In that case, it uses the byte order of the current default BFD, which happened to be big-endian on that GDB build, and the gdbarch returned is a big-endian one. The instruction used for the 32-bits part of the test is written in little-endian form, so GDB fails to decode the instruction properly. Since ARM supports both endiannesses, and it should be possible to debug using an host of both endiannesses, I changed the test to check with gdbarches of both endiannesses. gdb/ChangeLog: * arm-tdep.c (arm_record_test): Test with big and little endian gdbarch. --- gdb/arm-tdep.c | 106 ++++++++++++++++++++++++++++++--------------------------- 1 file changed, 56 insertions(+), 50 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index ef7e66b36a..840b82b57c 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -13247,70 +13247,76 @@ private: static void arm_record_test (void) { - struct gdbarch_info info; - gdbarch_info_init (&info); - info.bfd_arch_info = bfd_scan_arch ("arm"); + std::array endiannesses{{ BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE }}; - struct gdbarch *gdbarch = gdbarch_find_by_info (info); + for (bfd_endian endian : endiannesses) + { + struct gdbarch_info info; + gdbarch_info_init (&info); + info.bfd_arch_info = bfd_scan_arch ("arm"); + info.byte_order = endian; + info.byte_order_for_code = endian; - SELF_CHECK (gdbarch != NULL); + struct gdbarch *gdbarch = gdbarch_find_by_info (info); - /* 16-bit Thumb instructions. */ - { - insn_decode_record arm_record; + SELF_CHECK (gdbarch != NULL); - memset (&arm_record, 0, sizeof (insn_decode_record)); - arm_record.gdbarch = gdbarch; + /* 16-bit Thumb instructions. */ + { + insn_decode_record arm_record; - static const uint16_t insns[] = { - /* db b2 uxtb r3, r3 */ - 0xb2db, - /* cd 58 ldr r5, [r1, r3] */ - 0x58cd, - }; + memset (&arm_record, 0, sizeof (insn_decode_record)); + arm_record.gdbarch = gdbarch; - enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch); - instruction_reader_thumb reader (endian, insns); - int ret = decode_insn (reader, &arm_record, THUMB_RECORD, - THUMB_INSN_SIZE_BYTES); + static const uint16_t insns[] = { + /* db b2 uxtb r3, r3 */ + 0xb2db, + /* cd 58 ldr r5, [r1, r3] */ + 0x58cd, + }; - SELF_CHECK (ret == 0); - SELF_CHECK (arm_record.mem_rec_count == 0); - SELF_CHECK (arm_record.reg_rec_count == 1); - SELF_CHECK (arm_record.arm_regs[0] == 3); + instruction_reader_thumb reader (endian, insns); + int ret = decode_insn (reader, &arm_record, THUMB_RECORD, + THUMB_INSN_SIZE_BYTES); - arm_record.this_addr += 2; - ret = decode_insn (reader, &arm_record, THUMB_RECORD, - THUMB_INSN_SIZE_BYTES); + SELF_CHECK (ret == 0); + SELF_CHECK (arm_record.mem_rec_count == 0); + SELF_CHECK (arm_record.reg_rec_count == 1); + SELF_CHECK (arm_record.arm_regs[0] == 3); - SELF_CHECK (ret == 0); - SELF_CHECK (arm_record.mem_rec_count == 0); - SELF_CHECK (arm_record.reg_rec_count == 1); - SELF_CHECK (arm_record.arm_regs[0] == 5); - } + arm_record.this_addr += 2; + ret = decode_insn (reader, &arm_record, THUMB_RECORD, + THUMB_INSN_SIZE_BYTES); - /* 32-bit Thumb-2 instructions. */ - { - insn_decode_record arm_record; + SELF_CHECK (ret == 0); + SELF_CHECK (arm_record.mem_rec_count == 0); + SELF_CHECK (arm_record.reg_rec_count == 1); + SELF_CHECK (arm_record.arm_regs[0] == 5); + } + + /* 32-bit Thumb-2 instructions. */ + { + insn_decode_record arm_record; - memset (&arm_record, 0, sizeof (insn_decode_record)); - arm_record.gdbarch = gdbarch; + memset (&arm_record, 0, sizeof (insn_decode_record)); + arm_record.gdbarch = gdbarch; - static const uint16_t insns[] = { - /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */ - 0xee1d, 0x7f70, - }; + /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */ + static const uint16_t insns[2][2] = { + { 0x7f70, 0xee1d }, /* big */ + { 0xee1d, 0x7f70 }, /* little */ + }; - enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch); - instruction_reader_thumb reader (endian, insns); - int ret = decode_insn (reader, &arm_record, THUMB2_RECORD, - THUMB2_INSN_SIZE_BYTES); + instruction_reader_thumb reader (endian, insns[endian]); + int ret = decode_insn (reader, &arm_record, THUMB2_RECORD, + THUMB2_INSN_SIZE_BYTES); - SELF_CHECK (ret == 0); - SELF_CHECK (arm_record.mem_rec_count == 0); - SELF_CHECK (arm_record.reg_rec_count == 1); - SELF_CHECK (arm_record.arm_regs[0] == 7); - } + SELF_CHECK (ret == 0); + SELF_CHECK (arm_record.mem_rec_count == 0); + SELF_CHECK (arm_record.reg_rec_count == 1); + SELF_CHECK (arm_record.arm_regs[0] == 7); + } + } } } // namespace selftests #endif /* GDB_SELF_TEST */