From patchwork Tue Mar 6 02:45:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 26203 Received: (qmail 87994 invoked by alias); 6 Mar 2018 02:46:04 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 87661 invoked by uid 89); 6 Mar 2018 02:45:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_PASS, TIME_LIMIT_EXCEEDED autolearn=unavailable version=3.3.2 spammy=ppr, PPR X-HELO: mail-vk0-f66.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=WQBbuDzJuKAE3akOAVyS4L+7iFvXCpUgnHPB0aaZDHk=; b=mz+7GCKGKPT9A0n4esygPziEztltqfBZvwXkZExGFd8ga3fdp2n6aOjAQZSeA2m2o6 /PfDeKvOB90xtUfH0LdbZqI0fG4VGtJtZrS5INCzcXv/1JlBCHp7Z85y78Etg8mZcSQ1 IIvw6KBIe4PJb3wScTSgsBKIpWyFRib5+QAuUD1IBzqGDMNMBaZ0U5UthkCF8yVDcTQa s99CYti62k4kebf+44A26MHNM+HtNm8sq7OUaFywQGC05wav2lkTLnuyky5bTERbtsQv uwMw8w02/hJe1ekSV9Ba2FKa/13hBgwz5rxnyAn3gmmtu4rMv9TGVUF+h8RJXH6mkQPi 3eBg== X-Gm-Message-State: APf1xPDbh3AZ9TFBTyfS6glC6NkpDHnof/10UVK3nbfE+NZFWkibp7YW jjx5AnHdv2bjGILlo7M6pOU7x7A2PdQ= X-Google-Smtp-Source: AG47ELvrJWL+6R6/a6rAC5yN6FDgNSJKmCYD9N12JAO3s0zwdaa6Oe3P8XiXg1nNoagshsV3X2mJAw== X-Received: by 10.31.107.145 with SMTP id k17mr11830474vki.198.1520304317426; Mon, 05 Mar 2018 18:45:17 -0800 (PST) Subject: Re: [PATCH] powerpc: Fix tst-set_ppr.c on 32-bit POWER7 To: libc-alpha@sourceware.org References: <20180302203931.30149-1-tuliom@linux.vnet.ibm.com> From: Adhemerval Zanella Message-ID: Date: Mon, 5 Mar 2018 23:45:13 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180302203931.30149-1-tuliom@linux.vnet.ibm.com> On 02/03/2018 17:39, Tulio Magno Quites Machado Filho wrote: > Instruction mfppr32 is categorized as phased-in in the POWER ISA 2.06, > which means that servers do not implement it. > It started to be available in POWER ISA 2.07. > > 2018-03-02 Tulio Magno Quites Machado Filho > > * sysdeps/powerpc/tst-set_ppr.c (do_test): Test for > PPC_FEATURE2_ARCH_2_07 before trying to read the PPR32 on a > POWER7 system. > > Signed-off-by: Tulio Magno Quites Machado Filho > --- > sysdeps/powerpc/tst-set_ppr.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/sysdeps/powerpc/tst-set_ppr.c b/sysdeps/powerpc/tst-set_ppr.c > index c4f8096..da8c4cd 100644 > --- a/sysdeps/powerpc/tst-set_ppr.c > +++ b/sysdeps/powerpc/tst-set_ppr.c > @@ -73,13 +73,21 @@ static int > do_test (void) > { > /* Check for the minimum required Power ISA to run these tests. */ > +#ifdef __powerpc64__ > if ((getauxval (AT_HWCAP) & PPC_FEATURE_ARCH_2_06) == 0) > { > printf ("Requires an environment that implements the Power ISA version" > " 2.06 or greater.\n"); > return EXIT_UNSUPPORTED; > } > - > +#else > + if ((getauxval (AT_HWCAP2) & PPC_FEATURE2_ARCH_2_07) == 0) > + { > + printf ("Requires an environment that implements the Power ISA version" > + " 2.07 or greater.\n"); > + return EXIT_UNSUPPORTED; > + } > +#endif > uint8_t rc = 0; > > #ifdef _ARCH_PWR8 > Unfortunately similar to tabort. issue I am seeing a build issue with unrecognised mppfr32 instruction with an e500 toolchain. I suggest you to add a similar build condition to avoid such instruction as: diff --git a/sysdeps/powerpc/tst-set_ppr.c b/sysdeps/powerpc/tst-set_ppr.c index c4f8096bf8..4da5335c12 100644 --- a/sysdeps/powerpc/tst-set_ppr.c +++ b/sysdeps/powerpc/tst-set_ppr.c @@ -26,13 +26,22 @@ #include #ifdef __powerpc64__ - typedef uint64_t ppr_t; -# define MFPPR "mfppr" - /* The thread priority value is obtained from bits 11:13. */ +typedef uint64_t ppr_t; +# ifdef _ARCH_PWR7 +# define MFPPR(ppr) asm volatile ("mfppr %0" : "=r"(ppr)) +/* The thread priority value is obtained from bits 11:13. */ +# else +# define MFPPR(ppr) (ppr) = 0 +# endif # define EXTRACT_THREAD_PRIORITY(x) ((x >> 50) & 7) #else - typedef uint32_t ppr_t; -# define MFPPR "mfppr32" +typedef uint32_t ppr_t; +# ifdef _ARCH_PWR8 +# define MFPPR(ppr) asm volatile ("mfppr32 %0" : "=r"(ppr)) +/* The thread priority value is obtained from bits 11:13. */ +# else +# define MFPPR(ppr) (ppr) = 0 +# endif /* For 32-bit, the upper 32 bits of the Program Priority Register (PPR) are used, so the thread priority value is obtained from bits 43:46. */ # define EXTRACT_THREAD_PRIORITY(x) ((x >> 18) & 7) @@ -42,10 +51,8 @@ static __inline__ ppr_t get_thread_priority (void) { - /* Read the PPR. */ ppr_t ppr; - asm volatile (MFPPR" %0" : "=r"(ppr)); - /* Return the thread priority value. */ + MFPPR (ppr); return EXTRACT_THREAD_PRIORITY (ppr); }