From patchwork Fri Feb 9 15:03:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 25888 Received: (qmail 114306 invoked by alias); 9 Feb 2018 15:03:21 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 114295 invoked by uid 89); 9 Feb 2018 15:03:20 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy=prereq X-HELO: EUR01-DB5-obe.outbound.protection.outlook.com From: Wilco Dijkstra To: Szabolcs Nagy , "libc-alpha@sourceware.org" CC: nd Subject: Re: [PATCH][AArch64] Use builtins for fpcr/fpsr Date: Fri, 9 Feb 2018 15:03:14 +0000 Message-ID: References: , <5A60A7BF.6090000@arm.com>, In-Reply-To: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB6PR0801MB2037; 7:YDWKAz0cfS5/j++eESUi1ySZeM9dr/Q7MGiJ4DipLLmFMWR8GXHPOTFzoUuzjQDpxbNrcuF2NF64duWTGK+VAMZvgO0UbnwU/BxI5GGUWs9FlSlA9zYt54CcC0OrUBeG1th+Hpj/tQKcuVESF11hVS3D8iRJ1gHriROnxyCMfT799sFwK+wKx6gak2tnqURODome1loqw3z4c29lRP3t7Str5sFdRlQixQujm30uH0cGAE3geSM8D5w2bNm4+Z9C x-ms-exchange-antispam-srfa-diagnostics: SSOS;SSOR; x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 8bcd1b3e-c86e-4cb9-92e9-08d56fce3e65 x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(48565401081)(5600026)(4604075)(3008032)(2017052603307)(7153060)(7193020); SRVR:DB6PR0801MB2037; x-ms-traffictypediagnostic: DB6PR0801MB2037: nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040501)(2401047)(5005006)(8121501046)(10201501046)(3231101)(2400082)(944501161)(93006095)(93001095)(3002001)(6055026)(6041288)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123564045)(20161123562045)(20161123560045)(6072148)(201708071742011); SRVR:DB6PR0801MB2037; BCL:0; PCL:0; RULEID:; SRVR:DB6PR0801MB2037; x-forefront-prvs: 057859F9C5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(366004)(346002)(396003)(376002)(39380400002)(189003)(199004)(54534003)(377424004)(575784001)(229853002)(6436002)(55016002)(316002)(68736007)(72206003)(14454004)(86362001)(99286004)(81156014)(478600001)(102836004)(81166006)(2950100002)(5660300001)(8676002)(8936002)(97736004)(110136005)(9686003)(4326008)(6506007)(76176011)(25786009)(66066001)(26005)(53546011)(5250100002)(53936002)(33656002)(105586002)(6246003)(2906002)(3660700001)(3280700002)(2501003)(106356001)(7736002)(74316002)(6116002)(3846002)(2900100001)(7696005)(305945005); DIR:OUT; SFP:1101; SCL:1; SRVR:DB6PR0801MB2037; H:DB6PR0801MB2053.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: s91OUzUS7FoU2J6k97Ik06KNw/fpoyvn6DOJfxuGAkaQpakJT7xNdfrnJKbn+P53c5AQW3VtvIfDXCiALHAd9A== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8bcd1b3e-c86e-4cb9-92e9-08d56fce3e65 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Feb 2018 15:03:14.2802 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0801MB2037 ping From: Wilco Dijkstra Sent: 19 January 2018 13:18 To: Szabolcs Nagy; libc-alpha@sourceware.org Cc: nd Subject: Re: [PATCH][AArch64] Use builtins for fpcr/fpsr   Szabolcs Nagy wrote: > this will have to wait for the next release, but please > increase the gcc prereq to 6.0 because i see ice on gcc-5: aarch64-none-linux-gnu-gcc ../sysdeps/aarch64/fpu/fesetenv.c -c [..] ../sysdeps/aarch64/fpu/fesetenv.c: In function '__fesetenv': ../sysdeps/aarch64/fpu/fesetenv.c:75:1: error: unrecognizable insn:  }  ^ (insn 23 22 4 6 (unspec_volatile [             (mem:SI (plus:DI (reg/v/f:DI 85 [ envp ])                     (const_int 4 [0x4])) [2 envp_8(D)->__fpsr+0 S4 A32])         ] UNSPECV_SET_FPSR) ../sysdeps/aarch64/fpu/fesetenv.c:41 -1      (nil)) ../sysdeps/aarch64/fpu/fesetenv.c:75:1: internal compiler error: in extract_insn, at recog.c:2343 Looks like it's merging a MEM into a register operand. Since GCC5 is no longer supported I've updated it to GCC6: Since GCC has support for accessing FPSR/FPCR, use them when possible so that the asm instructions can be removed eventually.  Although GCC 5 supports the builtins, it has an optimization bug, so use them from GCC 6 onwards. GLIBC build and test OK. ChangeLog: 2018-01-19  Wilco Dijkstra          * sysdeps/aarch64/fpu/fpu_control.h: Use builtins for accessing FPCR/FPSR. diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h index 570e3dca78adbbccdc21ca879c582e1e09196f2d..d0cc5afc9faf42249a45b7f6b24a374f944998fd 100644 --- a/sysdeps/aarch64/fpu/fpu_control.h +++ b/sysdeps/aarch64/fpu/fpu_control.h @@ -21,17 +21,24 @@    /* Macros for accessing the FPCR and FPSR.  */   -#define _FPU_GETCW(fpcr) \ +#if __GNUC_PREREQ (6,0) +# define _FPU_GETCW(fpcr) (fpcr = __builtin_aarch64_get_fpcr ()) +# define _FPU_SETCW(fpcr) __builtin_aarch64_set_fpcr (fpcr) +# define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ()) +# define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr) +#else +# define _FPU_GETCW(fpcr) \    __asm__ __volatile__ ("mrs   %0, fpcr" : "=r" (fpcr))   -#define _FPU_SETCW(fpcr) \ +# define _FPU_SETCW(fpcr) \    __asm__ __volatile__ ("msr   fpcr, %0" : : "r" (fpcr))   -#define _FPU_GETFPSR(fpsr) \ +# define _FPU_GETFPSR(fpsr) \    __asm__ __volatile__ ("mrs   %0, fpsr" : "=r" (fpsr))   -#define _FPU_SETFPSR(fpsr) \ +# define _FPU_SETFPSR(fpsr) \    __asm__ __volatile__ ("msr   fpsr, %0" : : "r" (fpsr)) +#endif    /* Reserved bits should be preserved when modifying register     contents. These two masks indicate which bits in each of FPCR and