From patchwork Tue Jan 9 11:38:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 25285 Received: (qmail 94834 invoked by alias); 9 Jan 2018 11:38:15 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 94823 invoked by uid 89); 9 Jan 2018 11:38:15 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:1548, mrs, reserved X-HELO: EUR03-AM5-obe.outbound.protection.outlook.com From: Wilco Dijkstra To: "libc-alpha@sourceware.org" CC: nd Subject: [PATCH][AArch64] Use builtins for fpcr/fpsr Date: Tue, 9 Jan 2018 11:38:03 +0000 Message-ID: x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB6PR0801MB2054; 7:VCUwZD6Oy/gUDiuj/6L9hITWaPAoawBt1qMJM22yjqjLVSgF3tdfK1olJFjzrAA7ZkQzEj0QyjClWz2UkPvxPx6Yi91islrk5YhhOLRKY3DO/IJmEqWECZZXvK6JBvhc4FNRVXDmJY2lDnoiR4ao7Z5vzCzChNaGW9nSs38VjjNtJ/vf+wfWmRyWO6cTUwNR1Kb1GwCtF1DQI7J6q1k+98QjAyl/HH8/yiMtzYtJ4t6KaBQ9ze9nwLfIozVV0nTs x-ms-exchange-antispam-srfa-diagnostics: SSOS; x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 2f3d6315-a43d-4cd9-c329-08d557557204 x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(48565401081)(4534020)(4602075)(4627115)(201703031133081)(201702281549075)(5600026)(4604075)(3008032)(2017052603307)(7153060)(7193020); SRVR:DB6PR0801MB2054; x-ms-traffictypediagnostic: DB6PR0801MB2054: nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040470)(2401047)(5005006)(8121501046)(3002001)(3231023)(944501110)(10201501046)(93006095)(93001095)(6055026)(6041268)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123564045)(20161123558120)(20161123560045)(20161123562045)(6072148)(201708071742011); SRVR:DB6PR0801MB2054; BCL:0; PCL:0; RULEID:(100000803101)(100110400095); SRVR:DB6PR0801MB2054; x-forefront-prvs: 0547116B72 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(396003)(39380400002)(376002)(39860400002)(366004)(346002)(377424004)(54534003)(199004)(189003)(478600001)(25786009)(33656002)(6116002)(14454004)(6346003)(6916009)(72206003)(6506007)(2351001)(86362001)(5660300001)(2900100001)(97736004)(3846002)(68736007)(66066001)(74316002)(7696005)(81166006)(2501003)(316002)(4326008)(305945005)(99286004)(8676002)(3660700001)(3280700002)(105586002)(81156014)(53936002)(2906002)(102836004)(55016002)(5640700003)(6436002)(106356001)(5250100002)(8936002)(7736002)(9686003); DIR:OUT; SFP:1101; SCL:1; SRVR:DB6PR0801MB2054; H:DB6PR0801MB2053.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-microsoft-antispam-message-info: BseXWkCeIjn+fL7D8wCm1k2sZXI6qm/AGFq0LTjsnYk9jBjEL4FkLVJrjRlLiYur2gpKRAgw9XQ3w01UvvsDWg== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2f3d6315-a43d-4cd9-c329-08d557557204 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jan 2018 11:38:03.4857 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0801MB2054 Since GCC 5 has builtin support for accessing FPSR/FPCR, use them when possible so that the asm instructions can be removed eventually. GLIBC build and test OK. ChangeLog: 2018-01-09 Wilco Dijkstra * sysdeps/aarch64/fpu/fpu_control.h: Use builtins for accessing FPCR/FPSR. diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h index 570e3dca78adbbccdc21ca879c582e1e09196f2d..d7ed28e3c1d7bd4a89087604f80268c36c890c80 100644 --- a/sysdeps/aarch64/fpu/fpu_control.h +++ b/sysdeps/aarch64/fpu/fpu_control.h @@ -21,17 +21,24 @@ /* Macros for accessing the FPCR and FPSR. */ -#define _FPU_GETCW(fpcr) \ +#if __GNUC_PREREQ (5,0) +# define _FPU_GETCW(fpcr) (fpcr = __builtin_aarch64_get_fpcr ()) +# define _FPU_SETCW(fpcr) __builtin_aarch64_set_fpcr (fpcr) +# define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ()) +# define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr) +#else +# define _FPU_GETCW(fpcr) \ __asm__ __volatile__ ("mrs %0, fpcr" : "=r" (fpcr)) -#define _FPU_SETCW(fpcr) \ +# define _FPU_SETCW(fpcr) \ __asm__ __volatile__ ("msr fpcr, %0" : : "r" (fpcr)) -#define _FPU_GETFPSR(fpsr) \ +# define _FPU_GETFPSR(fpsr) \ __asm__ __volatile__ ("mrs %0, fpsr" : "=r" (fpsr)) -#define _FPU_SETFPSR(fpsr) \ +# define _FPU_SETFPSR(fpsr) \ __asm__ __volatile__ ("msr fpsr, %0" : : "r" (fpsr)) +#endif /* Reserved bits should be preserved when modifying register contents. These two masks indicate which bits in each of FPCR and