From patchwork Wed Oct 4 16:51:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Bowman X-Patchwork-Id: 23330 Received: (qmail 64233 invoked by alias); 4 Oct 2017 16:51:08 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 64221 invoked by uid 89); 4 Oct 2017 16:51:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=(unknown), Hx-languages-length:2618, family, HAccept-Language:en-GB X-HELO: smtp-out6.electric.net Received: from smtp-out6.electric.net (HELO smtp-out6.electric.net) (192.162.217.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 04 Oct 2017 16:51:06 +0000 Received: from 1dzmsx-0002ms-Vd by out6a.electric.net with emc1-ok (Exim 4.87) (envelope-from ) id 1dzmsy-0002oX-TO for gdb-patches@sourceware.org; Wed, 04 Oct 2017 09:51:04 -0700 Received: by emcmailer; Wed, 04 Oct 2017 09:51:04 -0700 Received: from [188.39.184.226] (helo=glaexch1.ftdichip.com) by out6a.electric.net with esmtps (TLSv1:AES128-SHA:128) (Exim 4.87) (envelope-from ) id 1dzmsx-0002ms-Vd for gdb-patches@sourceware.org; Wed, 04 Oct 2017 09:51:03 -0700 Received: from GLAEXCH1.ftdi.local ([172.16.0.121]) by glaexch3 ([172.16.0.161]) with mapi id 14.01.0438.000; Wed, 4 Oct 2017 17:51:03 +0100 From: James Bowman To: "gdb-patches@sourceware.org" Subject: [PATCH] FT32: support for FT32B processor - part 1 Date: Wed, 4 Oct 2017 16:51:02 +0000 Message-ID: <2BB0A51F073B384698CACFD1D5A30FCC0DED1F49@glaexch1> MIME-Version: 1.0 X-Outbound-IP: 188.39.184.226 X-Env-From: james.bowman@ftdichip.com X-Proto: esmtps X-Revdns: 188-39-184-226.static.enta.net X-TLS: TLSv1:AES128-SHA:128 X-Authenticated_ID: X-PolicySMART: 10711027 FT32B is a new FT32 family member. It has a code compression scheme, which requires the use of linker relaxations. The change is quite large, so submission is in several parts. Part 1 adds a 15-bit instruction field, and CPU-specific functions for the code compression that are used in binutils and GDB. This patch contains the gdb changes. The corresponding binutils patch is https://sourceware.org/ml/binutils/2017-10/msg00010.html OK to commit? James. gdb/ChangeLog: 2017-10-04 James Bowman * sim/ft32/interp.c (step_once): Replace FT32_FLD_K8 with K15. diff --git a/sim/ft32/interp.c b/sim/ft32/interp.c index b6fedc1..3bc08ee 100644 --- a/sim/ft32/interp.c +++ b/sim/ft32/interp.c @@ -332,7 +332,7 @@ step_once (SIM_DESC sd) uint32_t pa; uint32_t aa; uint32_t k16; - uint32_t k8; + uint32_t k15; uint32_t al; uint32_t r_1v; uint32_t rimmv; @@ -372,7 +372,11 @@ step_once (SIM_DESC sd) pa = (inst >> FT32_FLD_PA_BIT) & LSBS (FT32_FLD_PA_SIZ); aa = (inst >> FT32_FLD_AA_BIT) & LSBS (FT32_FLD_AA_SIZ); k16 = (inst >> FT32_FLD_K16_BIT) & LSBS (FT32_FLD_K16_SIZ); - k8 = nsigned (8, (inst >> FT32_FLD_K8_BIT) & LSBS (FT32_FLD_K8_SIZ)); + k15 = (inst >> FT32_FLD_K15_BIT) & LSBS (FT32_FLD_K15_SIZ); + if (k15 & 0x80) + k15 ^= 0x7f00; + if (k15 & 0x4000) + k15 -= 0x8000; al = (inst >> FT32_FLD_AL_BIT) & LSBS (FT32_FLD_AL_SIZ); r_1v = cpu->state.regs[r_1]; @@ -499,7 +503,7 @@ step_once (SIM_DESC sd) break; case FT32_PAT_LPMI: - cpu->state.regs[r_d] = ft32_read_item (sd, dw, cpu->state.regs[r_1] + k8); + cpu->state.regs[r_d] = ft32_read_item (sd, dw, cpu->state.regs[r_1] + k15); cpu->state.cycles += 1; break; @@ -508,7 +512,7 @@ step_once (SIM_DESC sd) break; case FT32_PAT_STI: - cpu_mem_write (sd, dw, cpu->state.regs[r_d] + k8, cpu->state.regs[r_1]); + cpu_mem_write (sd, dw, cpu->state.regs[r_d] + k15, cpu->state.regs[r_1]); break; case FT32_PAT_LDA: @@ -517,7 +521,7 @@ step_once (SIM_DESC sd) break; case FT32_PAT_LDI: - cpu->state.regs[r_d] = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k8); + cpu->state.regs[r_d] = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15); cpu->state.cycles += 1; break; @@ -534,8 +538,8 @@ step_once (SIM_DESC sd) case FT32_PAT_EXI: { uint32_t tmp; - tmp = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k8); - cpu_mem_write (sd, dw, cpu->state.regs[r_1] + k8, cpu->state.regs[r_d]); + tmp = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15); + cpu_mem_write (sd, dw, cpu->state.regs[r_1] + k15, cpu->state.regs[r_d]); cpu->state.regs[r_d] = tmp; cpu->state.cycles += 1; }