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Message-ID: <1502215837.3962.127.camel@cavium.com> Subject: Re: [PATCH 3/4] Add ILP32 support to aarch64 From: Steve Ellcey Reply-To: sellcey@cavium.com To: Szabolcs Nagy , Joseph Myers , Wilco Dijkstra Cc: nd@arm.com, "Ellcey, Steve" , "libc-alpha@sourceware.org" Date: Tue, 08 Aug 2017 11:10:37 -0700 In-Reply-To: <5989D25B.7000209@arm.com> References: <1501888532.3962.92.camel@cavium.com> <5989D25B.7000209@arm.com> Mime-Version: 1.0 X-ClientProxiedBy: MWHPR2201CA0004.namprd22.prod.outlook.com (10.174.164.17) To MWHPR07MB3551.namprd07.prod.outlook.com (10.164.192.140) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 285f2a0a-8e8d-4338-e061-08d4de88c6e9 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(300000503095)(300135400095)(49563074)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); 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MWHPR07MB3551; 6:Ft/tH8vZvsif3o08JOLUexoAlAY8/uxY8DSf7KLvmKBkFeIxSzXDVyp7vtYJaEvUt4Uo/sCVXTVS7CZASiVL8pPmeR71bKTinnEyQZRaKN2btE3ww71avq9K7+nBhUkhI3+/WK17sGjqeooccJz9iCNfYTo03lUA4jGze1Y/0KHdbI31HY2fa+ORAcVt4J3vk1UmbptzetiDCOf9lwJABp8fl+aS/hcNYFA6RnLW0tUl/y36P9dOE/1NoB0140PJ1wMCeNUX/VCU6yDa5fgwb9TAWs8bGfL1f4nJduwS4bLbCBp9uqAGsTR1JIqwvFN5IppZJ0MDnFywL0IIYFMXLg==; 5:3KFu8cckcKWABRAcPmpmBkMjAh01kEb/m3uaUadArmliejuqM/6/oGOIN1Dq7znYgTW1TgxAqN2V5gsjRRXmpv05WU4axUmcwxHsY4Hm+oYhJZopVgSJhFifNE7q0jWuSBADl/Bq9UIfMEPuaLBxwA==; 24:DTmPjon5yMbW/3+ed2gPHXK0fX99263ubSdXdUU1jdKAwXbNziGEb94TfZ2RKpN2WBIPfRZlmxp/tnGFQo4x08aZSPa4XlPgwO76HgdFN0c=; 7:XgHiO99sixg/vYE1vt8WRkgVQm+j4PImyh/ZuM2sdpYazMJyJtnZeIRKMs/RGxxT1vE1G3jFc0zw2DfWYk3LjjNXjYTqRZdzNhsAr4upCtON8HhAIFMybftdIjJ9P6n0uuIYStT+kNTFp6RxhHhI9bxnzkA2tsmFoOB/moVxIst3qWvib9Fg8TloCKr6f7l6RpGGSC/Ekaz+3bD24jKg8eTg+eadgFCDJn2/UV4br6k= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2017 18:10:39.7873 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR07MB3551 On Tue, 2017-08-08 at 16:01 +0100, Szabolcs Nagy wrote: >  > > +#if IREG_SIZE == 64 && OREG_SIZE == 32 > > +  if (__builtin_fabs (x) > INT32_MAX - 2) > i don't understand the -2 here. I was confused and trying to handle the fact that fabs(INT32_MIN) != INT32_MAX.  I have removed the -2 and am just comparing to INT32_MAX and that seems to work fine.  Since fabs(INT32_MIN) is greater than INT32_MAX we may unnecessarily enter this if statement for values between  INT32_MIN and INT32_MIN+1 but that should not cause any failures, just a slowdown. > > +    { > > +      /* Converting large values to a 32 bit in may cause the > > frintx/fcvtza > s/in/int/ Fixed that. > > +      invalid_p = libc_fetestexcept (FE_INVALID); > > +      inexact_p = libc_fetestexcept (FE_INEXACT); > multiple flags can be tested/raised in a single call. Good point.  I changed this to one call and saved the flags in an integer variable for checking later. > > +      libc_fesetenv (&env); > > + > > +      if (invalid_p) > > + feraiseexcept (FE_INVALID); > > +      else if (inexact_p) > > + feraiseexcept (FE_INEXACT); > > + > i think correct trapping is not guaranteed by glibc, > only correct status flags when the function returns, > so spurious inexact is not a problem if it is already > raised, and then i expect better code gen for the > inexact clearing approach: > > if (fabs (x) > INT32_MAX && fetestexcept (FE_INEXACT) == 0) >   { >     asm (...); >     if (fetestexcept (FE_INVALID|FE_INEXACT) == > (FE_INVALID|FE_INEXACT)) >       feclearexcept (FE_INEXACT); >   } > else >   asm (...); As you mentioned in your followup email, we have to worry about FE_INVALID being set on entry too.  I have attached an updated version of my patch. Steve Ellcey sellcey@cavium.com 2017-08-08  Steve Ellcey   * sysdeps/aarch64/fpu/s_llrint.c (OREG_SIZE): New macro. * sysdeps/aarch64/fpu/s_llround.c (OREG_SIZE): Likewise. * sysdeps/aarch64/fpu/s_llrintf.c (OREGS, IREGS): Remove. (IREG_SIZE, OREG_SIZE): New macros. * sysdeps/aarch64/fpu/s_llroundf.c: (OREGS, IREGS): Remove. (IREG_SIZE, OREG_SIZE): New macros. * sysdeps/aarch64/fpu/s_lrintf.c (IREGS): Remove. (IREG_SIZE): New macro. * sysdeps/aarch64/fpu/s_lroundf.c (IREGS): Remove. (IREG_SIZE): New macro. * sysdeps/aarch64/fpu/s_lrint.c (math_private.h, fenv.h, stdint.h): New includes. (IREG_SIZE, OREG_SIZE): Initialize if not already set. (OREGS, IREGS): Set based on IREG_SIZE and OREG_SIZE. (__CONCATX): Handle exceptions correctly on large values that may set FE_INVALID. * sysdeps/aarch64/fpu/s_lround.c (IREG_SIZE, OREG_SIZE): Initialize if not already set.         (OREGS, IREGS): Set based on IREG_SIZE and OREG_SIZE. diff --git a/sysdeps/aarch64/fpu/s_llrint.c b/sysdeps/aarch64/fpu/s_llrint.c index c0d0d0e..57821c0 100644 --- a/sysdeps/aarch64/fpu/s_llrint.c +++ b/sysdeps/aarch64/fpu/s_llrint.c @@ -18,4 +18,5 @@ #define FUNC llrint #define OTYPE long long int +#define OREG_SIZE 64 #include diff --git a/sysdeps/aarch64/fpu/s_llrintf.c b/sysdeps/aarch64/fpu/s_llrintf.c index 67724c6..98ed4f8 100644 --- a/sysdeps/aarch64/fpu/s_llrintf.c +++ b/sysdeps/aarch64/fpu/s_llrintf.c @@ -18,6 +18,7 @@ #define FUNC llrintf #define ITYPE float -#define IREGS "s" +#define IREG_SIZE 32 #define OTYPE long long int +#define OREG_SIZE 64 #include diff --git a/sysdeps/aarch64/fpu/s_llround.c b/sysdeps/aarch64/fpu/s_llround.c index ed4b192..ef7aedf 100644 --- a/sysdeps/aarch64/fpu/s_llround.c +++ b/sysdeps/aarch64/fpu/s_llround.c @@ -18,4 +18,5 @@ #define FUNC llround #define OTYPE long long int +#define OREG_SIZE 64 #include diff --git a/sysdeps/aarch64/fpu/s_llroundf.c b/sysdeps/aarch64/fpu/s_llroundf.c index 360ce8b..294f0f4 100644 --- a/sysdeps/aarch64/fpu/s_llroundf.c +++ b/sysdeps/aarch64/fpu/s_llroundf.c @@ -18,6 +18,7 @@ #define FUNC llroundf #define ITYPE float -#define IREGS "s" +#define IREG_SIZE 32 #define OTYPE long long int +#define OREG_SIZE 64 #include diff --git a/sysdeps/aarch64/fpu/s_lrint.c b/sysdeps/aarch64/fpu/s_lrint.c index 8c61a03..ed0135c 100644 --- a/sysdeps/aarch64/fpu/s_lrint.c +++ b/sysdeps/aarch64/fpu/s_lrint.c @@ -16,7 +16,10 @@ License along with the GNU C Library; if not, see . */ +#include #include +#include +#include #ifndef FUNC # define FUNC lrint @@ -24,18 +27,37 @@ #ifndef ITYPE # define ITYPE double -# define IREGS "d" +# define IREG_SIZE 64 #else -# ifndef IREGS -# error IREGS not defined +# ifndef IREG_SIZE +# error IREG_SIZE not defined # endif #endif #ifndef OTYPE # define OTYPE long int +# ifdef __ILP32__ +# define OREG_SIZE 32 +# else +# define OREG_SIZE 64 +# endif +#else +# ifndef OREG_SIZE +# error OREG_SIZE not defined +# endif +#endif + +#if IREG_SIZE == 32 +# define IREGS "s" +#else +# define IREGS "d" #endif -#define OREGS "x" +#if OREG_SIZE == 32 +# define OREGS "w" +#else +# define OREGS "x" +#endif #define __CONCATX(a,b) __CONCAT(a,b) @@ -44,6 +66,32 @@ __CONCATX(__,FUNC) (ITYPE x) { OTYPE result; ITYPE temp; + +#if IREG_SIZE == 64 && OREG_SIZE == 32 + if (__builtin_fabs (x) > INT32_MAX) + { + /* Converting large values to a 32 bit int may cause the frintx/fcvtza + sequence to set both FE_INVALID and FE_INEXACT. To avoid this + we save and restore the FE and only set one or the other. */ + + fenv_t env; + int feflags; + + libc_feholdexcept (&env); + asm ( "frintx" "\t%" IREGS "1, %" IREGS "2\n\t" + "fcvtzs" "\t%" OREGS "0, %" IREGS "1" + : "=r" (result), "=w" (temp) : "w" (x) ); + feflags = libc_fetestexcept (FE_INVALID | FE_INEXACT); + libc_fesetenv (&env); + + if (feflags & FE_INVALID) + feraiseexcept (FE_INVALID); + else if (feflags & FE_INEXACT) + feraiseexcept (FE_INEXACT); + + return result; + } +#endif asm ( "frintx" "\t%" IREGS "1, %" IREGS "2\n\t" "fcvtzs" "\t%" OREGS "0, %" IREGS "1" : "=r" (result), "=w" (temp) : "w" (x) ); diff --git a/sysdeps/aarch64/fpu/s_lrintf.c b/sysdeps/aarch64/fpu/s_lrintf.c index a995e4b..2e73271 100644 --- a/sysdeps/aarch64/fpu/s_lrintf.c +++ b/sysdeps/aarch64/fpu/s_lrintf.c @@ -18,5 +18,5 @@ #define FUNC lrintf #define ITYPE float -#define IREGS "s" +#define IREG_SIZE 32 #include diff --git a/sysdeps/aarch64/fpu/s_lround.c b/sysdeps/aarch64/fpu/s_lround.c index 9be9e7f..1f77d82 100644 --- a/sysdeps/aarch64/fpu/s_lround.c +++ b/sysdeps/aarch64/fpu/s_lround.c @@ -24,18 +24,37 @@ #ifndef ITYPE # define ITYPE double -# define IREGS "d" +# define IREG_SIZE 64 #else -# ifndef IREGS -# error IREGS not defined +# ifndef IREG_SIZE +# error IREG_SIZE not defined # endif #endif #ifndef OTYPE # define OTYPE long int +# ifdef __ILP32__ +# define OREG_SIZE 32 +# else +# define OREG_SIZE 64 +# endif +#else +# ifndef OREG_SIZE +# error OREG_SIZE not defined +# endif +#endif + +#if IREG_SIZE == 32 +# define IREGS "s" +#else +# define IREGS "d" #endif -#define OREGS "x" +#if OREG_SIZE == 32 +# define OREGS "w" +#else +# define OREGS "x" +#endif #define __CONCATX(a,b) __CONCAT(a,b) diff --git a/sysdeps/aarch64/fpu/s_lroundf.c b/sysdeps/aarch64/fpu/s_lroundf.c index 4a066d4..b30ddb6 100644 --- a/sysdeps/aarch64/fpu/s_lroundf.c +++ b/sysdeps/aarch64/fpu/s_lroundf.c @@ -18,5 +18,5 @@ #define FUNC lroundf #define ITYPE float -#define IREGS "s" +#define IREG_SIZE 32 #include