@@ -155,7 +155,7 @@ aarch64_get_mem_ptr (sim_cpu *cpu, uint64_t address)
an out-of-memory condition by noticing a stack/heap collision.
The heap starts at the end of loaded memory and carries on up
- to an arbitary 2Gb limit. */
+ to an arbitrary 2Gb limit. */
uint64_t
aarch64_get_heap_start (sim_cpu *cpu)
@@ -1695,7 +1695,7 @@ set_flags_for_add64 (sim_cpu *cpu, uint64_t value1, uint64_t value2)
}
else
{
- /* Postive plus positive - overflow has happened if the
+ /* Positive plus positive - overflow has happened if the
result is smaller than either of the operands. */
if (result < value1 || result < value2)
flags |= V | C;
@@ -131,7 +131,7 @@ check_cp15_access (ARMul_State * state,
return ARMul_CANT;
break;
case 7:
- /* Permissable combinations:
+ /* Permissible combinations:
Opcode_2 CRm
0 5
0 6
@@ -154,7 +154,7 @@ check_cp15_access (ARMul_State * state,
break;
case 8:
- /* Permissable combinations:
+ /* Permissible combinations:
Opcode_2 CRm
0 5
0 6
@@ -229,7 +229,7 @@ write_cp15_reg (ARMul_State * state,
/* Writes are not allowed. */
return;
- case 1: /* Auxillary Control. */
+ case 1: /* Auxiliary Control. */
/* Only BITS (5, 4) and BITS (1, 0) can be written. */
value &= 0x33;
break;
@@ -5974,7 +5974,7 @@ Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc)
hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
/* We now need to add all of these results together, taking
- care to propogate the carries from the additions. */
+ care to propagate the carries from the additions. */
RdLo = Add32 (lo, (mid1 << 16), &carry);
RdHi = carry;
RdLo = Add32 (RdLo, (mid2 << 16), &carry);
@@ -3539,7 +3539,7 @@ WXOR (ARMword instr)
return ARMul_DONE;
}
-/* This switch table is moved to a seperate function in order
+/* This switch table is moved to a separate function in order
to work around a compiler bug in the host compiler... */
static int
@@ -26,7 +26,7 @@
#include "hw-device.h"
#include "hw-tree.h"
-/* We keep the same inital structure layout with DMA enabled devices. */
+/* We keep the same initial structure layout with DMA enabled devices. */
struct dv_bfin {
bu32 base;
struct hw *dma_master;
@@ -570,7 +570,7 @@ _cec_raise (SIM_CPU *cpu, struct bfin_cec *cec, int ivg)
/* XXX: what happens with 'raise 0' ? */
SET_RETEREG (oldpc);
excp_to_sim_halt (sim_stopped, SIM_SIGTRAP);
- /* XXX: Need an easy way for gdb to signal it isnt here. */
+ /* XXX: Need an easy way for gdb to signal it isn't here. */
cec->ipend &= ~IVG_EMU_B;
break;
case IVG_RST:
@@ -62,10 +62,10 @@
<<glue>>: In addition to driving its output interrupt port with any
value written to an interrupt input port is stored in the
corresponding <<output>> register. Such input interrupts, however,
- are not propogated to an output interrupt port.
+ are not propagated to an output interrupt port.
<<glue-and>>: The bit-wise AND of the interrupt inputs is computed
- and then both stored in <<output>> register zero and propogated to
+ and then both stored in <<output>> register zero and propagated to
output interrupt output port zero.
@@ -52,7 +52,7 @@
DESCRIPTION
- Typical hardware dependant hack. This device allows the firmware
+ Typical hardware dependent hack. This device allows the firmware
to gain access to all the things the firmware needs (but the OS
doesn't).
@@ -104,8 +104,8 @@
zero value to this register clears the countdown timer. Writing a
non-zero 32 bit big-endian value to this register sets the
countdown timer to expire in VALUE ticks (ticks is target
- dependant). Reading the countdown register returns the last value
- writen.
+ dependent). Reading the countdown register returns the last value
+ written.
COUNTDOWN VALUE (read): Reading this 32 bit big-endian register
returns the number of ticks remaining until the countdown timer
@@ -115,7 +115,7 @@
interrupt source. Writing a 32 bit big-endian zero value to this
register clears the periodic timer. Writing a 32 bit non-zero
value to this register sets the periodic timer to triger every
- VALUE ticks (ticks is target dependant). Reading the timer
+ VALUE ticks (ticks is target dependent). Reading the timer
register returns the last value written.
TIMER VALUE (read): Reading this 32 bit big-endian register returns
@@ -23,7 +23,7 @@
#ifndef HW_BASE
#define HW_BASE
-/* Create a primative device */
+/* Create a primitive device */
struct hw *hw_create
(struct sim_state *sd,
@@ -167,7 +167,7 @@ typedef unsigned (hw_reset_method)
/* Hardware operations:
Connecting a parent to its children is a common bus. The parent
- node is described as the bus owner and is responisble for
+ node is described as the bus owner and is responsible for
co-ordinating bus operations. On the bus, a SPACE:ADDR pair is used
to specify an address. A device that is both a bus owner (parent)
and bus client (child) are referred to as a bridging device.
@@ -33,7 +33,7 @@
disks file system. The operations would be implemented using the
basic block I/O model provided by the disk.
- This model includes methods that faciliate the creation of device
+ This model includes methods that facilitate the creation of device
instance and (should a given device support it) standard operations
on those instances.
@@ -130,7 +130,7 @@ detach_hw_port_edge (struct hw *me,
&& old_edge->my_port == my_port)
{
if (old_edge->disposition == permenant_object)
- hw_abort (me, "attempt to delete permenant port edge");
+ hw_abort (me, "attempt to delete permanent port edge");
*list = old_edge->next;
hw_free (me, old_edge);
return;
@@ -477,7 +477,7 @@ count_entries (struct hw *current,
-/* parse: <address> ::= <token> ; device dependant */
+/* parse: <address> ::= <token> ; device dependent */
static const char *
parse_address (struct hw *current,
@@ -1273,7 +1273,7 @@ hw_tree_find_device (struct hw *root,
/* parse the path */
split_device_specifier (root, path_to_device, &spec);
if (spec.value != NULL)
- return NULL; /* something wierd */
+ return NULL; /* something weird */
/* now find it */
node = split_find_device (root, &spec);
@@ -453,7 +453,7 @@ do { \
#define ALU8_CARRY_BORROW_RESULT ((unsigned8) alu8_cr)
#define ALU8_OVERFLOW_RESULT ((unsigned8) alu8_vr)
-/* #define ALU8_END ????? - target dependant */
+/* #define ALU8_END ????? - target dependent */
@@ -485,7 +485,7 @@ do { \
#define ALU16_CARRY_BORROW_RESULT ((unsigned16) alu16_cr)
#define ALU16_OVERFLOW_RESULT ((unsigned16) alu16_vr)
-/* #define ALU16_END ????? - target dependant */
+/* #define ALU16_END ????? - target dependent */
@@ -88,12 +88,12 @@ frob_range (ADDR_RANGE *ar, address_word start, address_word end, int delete_p)
{
if (! delete_p)
{
- /* Try next range if current range preceeds new one and not
+ /* Try next range if current range precedes new one and not
adjacent or overlapping. */
if (asr->end < caller->start - 1)
goto next_range;
- /* Break out if new range preceeds current one and not
+ /* Break out if new range precedes current one and not
adjacent or overlapping. */
if (asr->start > caller->end + 1)
break;
@@ -120,11 +120,11 @@ frob_range (ADDR_RANGE *ar, address_word start, address_word end, int delete_p)
}
else /* deleting a range */
{
- /* Try next range if current range preceeds new one. */
+ /* Try next range if current range precedes new one. */
if (asr->end < caller->start)
goto next_range;
- /* Break out if new range preceeds current one. */
+ /* Break out if new range precedes current one. */
if (asr->start > caller->end)
break;
@@ -30,7 +30,7 @@
#include "config.h"
#endif
-/* Basic host dependant mess - hopefully <stdio.h> + <stdarg.h> will
+/* Basic host dependent mess - hopefully <stdio.h> + <stdarg.h> will
bring potential conflicts out in the open */
#include <stdarg.h>
@@ -441,7 +441,7 @@ INLINE_SIM_BITS(unsigned_word) MSEXTRACTED (unsigned_word val, int start, int st
/* move a single bit around */
-/* NB: the wierdness (N>O?N-O:0) is to stop a warning from GCC */
+/* NB: the weirdness (N>O?N-O:0) is to stop a warning from GCC */
#define _SHUFFLEDn(N, WORD, OLD, NEW) \
((OLD) < (NEW) \
? (((unsigned##N)(WORD) \
@@ -552,7 +552,7 @@ do { \
/* some rotate functions. The generic macro's ROT, ROTL, ROTR are
- intentionally omited. */
+ intentionally omitted. */
INLINE_SIM_BITS(unsigned8) ROT8 (unsigned8 val, int shift);
@@ -24,7 +24,7 @@
#define SIM_CONFIG_H
-/* Host dependant:
+/* Host dependent:
The CPP below defines information about the compilation host. In
particular it defines the macro's:
@@ -146,7 +146,7 @@ extern enum bfd_endian current_target_byte_order;
expect to see (VEA includes things like coherency and the time
base) while OEA is what an operating system expects to see. By
setting these to specific values, the build process is able to
- eliminate non relevent environment code.
+ eliminate non relevant environment code.
STATE_ENVIRONMENT(sd) specifies which of vea or oea is required for
the current runtime.
@@ -129,7 +129,7 @@ extern SIM_RC sim_core_install (SIM_DESC sd);
such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis
(OPTIONAL_BUFFER % 8) == (ADDR % 8)). It is defined to be a sub-optimal
hook that allows clients to do nasty things that the interface doesn't
- accomodate. */
+ accommodate. */
extern void sim_core_attach
(SIM_DESC sd,
@@ -160,7 +160,7 @@ extern void sim_core_detach
Transfer a variable sized block of raw data between the host and
target. Should any problems occur, the number of bytes
- successfully transfered is returned.
+ successfully transferred is returned.
No host/target byte endian conversion is performed. No xor-endian
conversion is performed.
@@ -206,7 +206,7 @@ extern void sim_core_set_xor
Transfer a variable sized block of raw data between the host and
target. Should any problems occur, the number of bytes
- successfully transfered is returned.
+ successfully transferred is returned.
No host/target byte endian conversion is performed. If applicable
(WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is*
@@ -244,11 +244,11 @@ extern void *sim_core_trans_addr
/* Fixed sized, processor oriented, read/write.
Transfer a fixed amout of memory between the host and target. The
- data transfered is translated from/to host to/from target byte
+ data transferred is translated from/to host to/from target byte
order (including xor endian). Should the transfer fail, the
operation shall abort (no return).
- ALIGNED assumes yhat the specified ADDRESS is correctly alligned
+ ALIGNED assumes yhat the specified ADDRESS is correctly aligned
for an N byte transfer (no alignment checks are made). Passing an
incorrectly aligned ADDRESS is erroneous.
@@ -131,7 +131,7 @@ extern void sim_engine_vabort
/* Called by the generic sim_resume to run the simulation within the
- above safty net.
+ above safety net.
An example implementation of sim_engine_run can be found in the
file sim-run.c */
@@ -140,7 +140,7 @@ extern void sim_events_schedule_after_signal
/* Schedule an event milli-seconds from NOW. The exact interpretation
- of wallclock is host dependant. */
+ of wallclock is host dependent. */
extern sim_event *sim_events_watch_clock
(SIM_DESC sd,
@@ -37,7 +37,7 @@
speed improvement (x3-x5). In the case of RISC (sparc) while the
performance gain isn't as great it is still significant.
- Each module is controled by the macro <module>_INLINE which can
+ Each module is controlled by the macro <module>_INLINE which can
have the values described below
0 (ZERO)
@@ -328,7 +328,7 @@ sim_io_poll_quit (SIM_DESC sd)
FIXME: Some completly new mechanism for handling the general
problem of asynchronous IO is needed.
- FIXME: This function does not supress the echoing (ECHO) of input.
+ FIXME: This function does not suppress the echoing (ECHO) of input.
Consequently polled input is always displayed.
FIXME: This function does not perform uncooked reads.
@@ -31,7 +31,7 @@ has_stepped (SIM_DESC sd,
}
-/* Generic resume - assumes the existance of sim_engine_run */
+/* Generic resume - assumes the existence of sim_engine_run */
void
sim_resume (SIM_DESC sd,
@@ -960,8 +960,8 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
{
if (PSW_RP && PC == RPT_E)
{
- /* Note: The behavour of a branch instruction at RPT_E
- is implementation dependant, this simulator takes the
+ /* Note: The behaviour of a branch instruction at RPT_E
+ is implementation dependent, this simulator takes the
branch. Branching to RPT_E is valid, the instruction
must be executed before the loop is taken. */
if (RPT_C == 1)
@@ -322,7 +322,7 @@ mul64 (uint32 n1, uint32 n2, uint32 *result_hi, uint32 *result_lo, int msigned)
hi = (((n1 >> 16) & 0xFFFF) * ((n2 >> 16) & 0xFFFF));
/* We now need to add all of these results together, taking care
- to propogate the carries from the additions: */
+ to propagate the carries from the additions: */
reg_lo = add32 (lo, (mid1 << 16), &carry);
reg_hi = carry;
reg_lo = add32 (reg_lo, (mid2 << 16), &carry);
@@ -20,7 +20,7 @@
FPU. IEEE trap handling is done as follows:
1. In the host, all IEEE traps are masked
2. After each simulated FPU instruction, check if any exception
- occured by reading the exception bits from the host FPU status
+ occurred by reading the exception bits from the host FPU status
register (get_accex()).
3. Propagate any exceptions to the simulated FSR.
4. Clear host exception bits.
@@ -121,7 +121,7 @@ struct pstate {
uint64 pwdtime; /* Cycles in power-down mode */
uint64 nstore; /* Number of load instructions */
uint64 nload; /* Number of store instructions */
- uint64 nannul; /* Number of annuled instructions */
+ uint64 nannul; /* Number of annulled instructions */
uint64 nbranch; /* Number of branch instructions */
uint32 ildreg; /* Destination of last load instruction */
uint64 ildtime; /* Last time point for load dependency */
@@ -266,7 +266,7 @@ enum frv_ec
/* FR-V Interrupt.
This struct contains enough information to describe a particular interrupt
- occurance. */
+ occurrence. */
struct frv_interrupt
{
enum frv_interrupt_kind kind;
@@ -282,7 +282,7 @@ struct frv_interrupt
extern struct frv_interrupt frv_interrupt_table[];
/* FR-V Interrupt State.
- Interrupts are queued during execution of parallel insns and the interupt(s)
+ Interrupts are queued during execution of parallel insns and the interrupt(s)
to be handled determined by analysing the queue after each VLIW insn. */
#define FRV_INTERRUPT_QUEUE_SIZE (4 * 4) /* 4 interrupts x 4 insns for now. */
@@ -830,7 +830,7 @@ set_exception_status_registers (
{
case FRV_DIVISION_EXCEPTION:
set_isr_exception_fields (current_cpu, item);
- /* fall thru to set reg_index. */
+ /* fall through to set reg_index. */
case FRV_COMMIT_EXCEPTION:
/* For fr550, always use ESR0. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
@@ -595,14 +595,14 @@ request_complete (SIM_CPU *cpu, CACHE_QUEUE_ELEMENT *q)
}
/* Run the insn and data caches through the given number of cycles, taking
- note of load requests which are fullfilled as a result. */
+ note of load requests which are fulfilled as a result. */
static void
run_caches (SIM_CPU *cpu, int cycles)
{
FRV_CACHE* data_cache = CPU_DATA_CACHE (cpu);
FRV_CACHE* insn_cache = CPU_INSN_CACHE (cpu);
int i;
- /* For each cycle, run the caches, noting which requests have been fullfilled
+ /* For each cycle, run the caches, noting which requests have been fulfilled
and submitting new requests on their designated cycles. */
for (i = 0; i < cycles; ++i)
{
@@ -6432,7 +6432,7 @@ frv_initialize_spr (SIM_CPU *current_cpu)
}
}
- /* Now explicitely set PSR in order to get the correct setting for PSR.S. */
+ /* Now explicitly set PSR in order to get the correct setting for PSR.S. */
spr_control = & control->spr[H_SPR_PSR];
save_mask = spr_control->read_only_mask;
spr_control->read_only_mask = 0;
@@ -6473,7 +6473,7 @@ frv_reset_spr (SIM_CPU *current_cpu)
}
}
- /* Now explicitely set PSR in order to get the correct setting for PSR.S. */
+ /* Now explicitly set PSR in order to get the correct setting for PSR.S. */
spr_control = & control->spr[H_SPR_PSR];
mask = spr_control->reset_mask;
new_val = GET_H_SPR (H_SPR_PSR) & ~mask;
@@ -773,7 +773,7 @@ frvbf_check_swap_address (SIM_CPU *current_cpu, SI address)
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
return;
- /* Adress must be aligned on a word boundary. */
+ /* Address must be aligned on a word boundary. */
if (address & 0x3)
frv_queue_data_access_exception_interrupt (current_cpu);
}
@@ -1906,7 +1906,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
case 0:
/*
* This opcode is a fake for when we get to an
- * instruction which hasnt been compiled
+ * instruction which hasn't been compiled
*/
compile (sd, pc);
goto top;
@@ -67,7 +67,7 @@ print_run_body (lf *file, gen_entry *table)
{
/* Output the function to execute real code:
- Unfortunatly, there are multiple cases to consider vis:
+ Unfortunately, there are multiple cases to consider vis:
<icache> X <smp>
@@ -102,7 +102,7 @@ In this case, we can take advantage of the fact that the current\n\
instruction address (CIA) does not need to be read from / written to\n\
the CPU object after the execution of an instruction.\n\
\n\
-Instead, CIA is only saved when the main loop exits. This occures\n\
+Instead, CIA is only saved when the main loop exits. This occurs\n\
when either sim_engine_halt or sim_engine_restart is called. Both of\n\
these functions save the current instruction address before halting /\n\
restarting the simulator.\n\
@@ -150,7 +150,7 @@ print_icache_extraction (lf *file,
switch (what_to_declare)
{
case undef_variables:
- /* We've finished with the #define value - destory it */
+ /* We've finished with the #define value - destroy it */
lf_indent_suppress (file);
lf_printf (file, "#undef %s\n", entry_name);
return;
@@ -630,7 +630,7 @@ print_icache_struct (lf *file, insn_table *isa, cache_entry *cache_rules)
else
{
/* alernativly, since no cache, emit a dummy definition for
- idecode_cache so that code refering to the type can still compile */
+ idecode_cache so that code referring to the type can still compile */
lf_printf (file, "typedef void %sidecode_cache;\n",
options.module.global.prefix.l);
}
@@ -629,7 +629,7 @@ idecode_declare_if_switch (lf *file, gen_entry *table, int depth, void *data)
{
print_idecode_switch_function_header (file,
table,
- 0 /*isnt function definition */ ,
+ 0 /* isn't function definition */ ,
0);
}
}
@@ -862,7 +862,7 @@ print_idecode_validate (lf *file,
proper.
The PowerPC spec requires a CSI after MSR[FP] is changed and when
- ever a CSI occures we flush the instruction cache. */
+ ever a CSI occurs we flush the instruction cache. */
{
if (filter_is_member (instruction->flags, "f"))
@@ -244,7 +244,7 @@ print_semantic_body (lf *file,
}
/* Architecture expects a REG to be zero. Instead of having to
- check every read to see if it is refering to that REG just zap it
+ check every read to see if it is referring to that REG just zap it
at the start of every instruction */
if (options.gen.zero_reg)
{
@@ -34,9 +34,9 @@
o cached - separate cracker and semantic
- Two independant functions are created. Firstly the
+ Two independent functions are created. Firstly the
function that cracks an instruction entering it into a
- cache and secondly the semantic function propper that
+ cache and secondly the semantic function proper that
uses the cache.
o cached - semantic + cracking semantic
@@ -47,7 +47,7 @@
cracker and the semantic function when there is a
cache miss).
- For each of these general forms, several refinements can occure:
+ For each of these general forms, several refinements can occur:
o do/don't duplicate/expand semantic functions
@@ -386,7 +386,7 @@ insn_list_insert (insn_list **cur_insn_ptr,
case report_duplicate_insns:
/* It would appear that we have two instructions with the
same constant field values across all words and bits.
- This error can also occure when insn_field_cmp() is
+ This error can also occur when insn_field_cmp() is
failing to differentiate between two instructions that
differ only in their conditional fields. */
warning (insn->line,
@@ -635,7 +635,7 @@ insns_bit_useless (insn_list *insns, decode_table *rule, int bit_nr)
/* Given only one constant value has been found, check through all
the instructions to see if at least one conditional makes it
- usefull */
+ useful */
if (value >= 0 && is_useless)
{
for (entry = insns; entry != NULL; entry = entry->next)
@@ -972,7 +972,7 @@ gen_entry_expand_opcode (gen_entry *table,
condition->field->last);
/* this is a requirement of
a conditonal field
- refering to another field */
+ referring to another field */
ASSERT ((condition->field->first -
condition->field->last) ==
(first_pos - last_pos));
@@ -482,7 +482,7 @@ print_itrace (lf *file, insn_entry * insn, int idecode)
{
/* NB: Here we escape each EOLN. This is so that the the compiler
treats a trace function call as a single line. Consequently any
- errors in the line are refered back to the same igen assembler
+ errors in the line are referred back to the same igen assembler
source line */
const char *phase = (idecode) ? "DECODE" : "INSN";
lf_printf (file, "\n");
@@ -136,7 +136,7 @@ struct _igen_decode_options
int combine;
/* Instruction expansion? Should the semantic code for each
- instruction, when the oportunity arrises, be expanded according
+ instruction, when the opportunity arrises, be expanded according
to the variable opcode files that the instruction decode process
renders constant */
int duplicate;
@@ -87,7 +87,7 @@
If an instruction field was found, enlarge the field size so that
it is forced to at least include bits starting from <force_first>
- (<force_last>). To stop this occuring, use <force_first> = <last>
+ (<force_last>). To stop this occurring, use <force_first> = <last>
+ 1 and <force_last> = <first> - 1.
<force_reserved>
@@ -99,7 +99,7 @@
Treat any contained register (string) fields as constant when
determining the instruction field. For the instruction decode (and
- controled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
+ controlled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
what would otherwize be non constant bits of an instruction.
<use_switch>
@@ -201,7 +201,7 @@ parse_insn_word (line_ref *line, char *string, int word_nr)
{
if (strlen_pos == 0)
{
- /* when the length/pos field is omited, an integer field
+ /* when the length/pos field is omitted, an integer field
is always binary */
unsigned64 val = 0;
int i;
@@ -409,7 +409,7 @@ parse_insn_words (insn_entry * insn, char *formats)
insn->word[i] = word;
}
- /* Go over all fields that have conditionals refering to other
+ /* Go over all fields that have conditionals referring to other
fields. Link the fields up. Verify that the two fields have the
same size. Verify that the two fields are different */
{
@@ -442,9 +442,9 @@ parse_insn_words (insn_entry * insn, char *formats)
&& strcmp (refered_field->val_string,
cond->string) == 0)
{
- /* found field being refered to by conditonal */
+ /* found field being referred to by conditonal */
cond->field = refered_field;
- /* check refered to and this field are
+ /* check referred to and this field are
the same size */
if (f->width != refered_field->width)
error (insn->line,
@@ -43,7 +43,7 @@ lf_file_references;
/* Open the file NAME for writing ("-" for stdout). Use REAL_NAME
- when refering to the opened file. Line number information (in the
+ when referring to the opened file. Line number information (in the
output) can be suppressed with FILE_REFERENCES ==
LF_OMIT_REFERENCES. TYPE is to determine the formatting of some of
the print messages below. */
@@ -93,7 +93,7 @@ do_uart_tx_event (struct hw *me, void *data)
hw_port_event (me, INT_PORT, 1);
}
- /* Indicate which interrupt has occured. */
+ /* Indicate which interrupt has occurred. */
uart->iir = MICOUART_IIR_TXRDY;
/* Indicate THR is empty. */
@@ -21,7 +21,7 @@
#ifndef DV_M32R_UART_H
#define DV_M32R_UART_H
-/* Should move these settings to a flag to the uart device, and the adresses to
+/* Should move these settings to a flag to the uart device, and the addresses to
the sim-model framework. */
/* Serial device addresses. */
@@ -87,7 +87,7 @@ struct m68hc11sio
is used to find the number of cpu cycles to send/receive a data. */
unsigned int data_length;
- /* Information about next character to be transmited. */
+ /* Information about next character to be transmitted. */
unsigned char tx_has_char;
unsigned char tx_char;
@@ -78,7 +78,7 @@ static const struct hw_port_descriptor m68hc11spi_ports[] =
/* SPI */
struct m68hc11spi
{
- /* Information about next character to be transmited. */
+ /* Information about next character to be transmitted. */
unsigned char tx_char;
int tx_bit;
unsigned char mode;
@@ -343,7 +343,7 @@ m68hc11tim_timer_event (struct hw *me, void *data)
compare = (cpu->ios[i] << 8) + cpu->ios[i + 1];
- /* See if compare is reached; handle wrap arround. */
+ /* See if compare is reached; handle wrap around. */
if ((compare >= tcnt_prev && compare <= tcnt && tcnt_prev < tcnt)
|| (compare >= tcnt_prev && tcnt_prev > tcnt)
|| (compare < tcnt && tcnt_prev > tcnt))
@@ -108,7 +108,7 @@ typedef enum {
/* For some MIPS targets, the HI/LO registers have certain timing
restrictions in that, for instance, a read of a HI register must be
- separated by at least three instructions from a preceeding read.
+ separated by at least three instructions from the preceding read.
The struct below is used to record the last access by each of A MT,
MF or other OP instruction to a HI/LO register. See mips.igen for
@@ -281,7 +281,7 @@ struct _sim_cpu {
#define simPCOC1 (1 << 18) /* COC[1] from previous */
#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
-#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
+#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occurred */
#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
#ifndef ENGINE_ISSUE_PREFIX_HOOK
@@ -180,7 +180,7 @@ sim_open (SIM_OPEN_KIND kind,
sim_hw_parse (sd, "/mn103cpu@0x20000000");
sim_hw_parse (sd, "/mn103cpu@0x20000000/reg 0x20000000 0x42");
- /* DEBUG: ACK output wired upto a glue device */
+ /* DEBUG: ACK output wired up to a glue device */
sim_hw_parse (sd, "/glue@0x20002000");
sim_hw_parse (sd, "/glue@0x20002000/reg 0x20002000 4");
sim_hw_parse (sd, "/mn103cpu > ack int0 /glue@0x20002000");
@@ -46,7 +46,7 @@ struct altivec_regs {
/* AltiVec endian helpers, wrong endian hosts vs targets need to be
sure to get the right bytes/halfs/words when the order matters.
Note that many AltiVec instructions do not depend on byte order and
- work on N independant bits of data. This is only for the
+ work on N independent bits of data. This is only for the
instructions that actually move data around. */
#if (WITH_HOST_BYTE_ORDER == BIG_ENDIAN)
@@ -90,7 +90,7 @@ typedef enum {
#include "inline.h"
-/* Basic host dependant mess - hopefully <stdio.h> + <stdarg.h> will
+/* Basic host dependent mess - hopefully <stdio.h> + <stdarg.h> will
bring potential conflicts out in the open */
#include <stdarg.h>
@@ -197,7 +197,7 @@ INLINE_BITS\
int stop);
/* move a single bit around */
-/* NB: the wierdness (N>O?N-O:0) is to stop a warning from GCC */
+/* NB: the weirdness (N>O?N-O:0) is to stop a warning from GCC */
#define _SHUFFLEDn(N, WORD, OLD, NEW) \
((OLD) < (NEW) \
? (((unsigned##N)(WORD) \
@@ -85,7 +85,7 @@ INLINE_CORE\
restarting it.
For callback maps it is possible to further order them by
- specifiying specifying a callback level (eg callback + 1).
+ specifying specifying a callback level (eg callback + 1).
When the core is resolving an access it searches each of the maps
in order. First raw-memory and then callback maps (in assending
@@ -119,7 +119,7 @@ INLINE_CORE\
The operation of mapping between an address and its destination
device or memory array is currently implemented using a simple
linked list. The posibility of replacing this list with a more
- powerfull data structure exists.
+ powerful data structure exists.
*/
@@ -170,8 +170,8 @@ INLINE_CORE\
/* Variable sized read/write
Transfer (zero) a variable size block of data between the host and
- target (possibly byte swapping it). Should any problems occure,
- the number of bytes actually transfered is returned. */
+ target (possibly byte swapping it). Should any problems occur,
+ the number of bytes actually transferred is returned. */
INLINE_CORE\
(unsigned) core_map_read_buffer
@@ -192,7 +192,7 @@ INLINE_CORE\
Transfer a fixed amout of memory between the host and target. The
memory always being translated and the operation always aborting
- should a problem occure */
+ should a problem occur */
#define DECLARE_CORE_WRITE_N(N) \
INLINE_CORE\
@@ -276,7 +276,7 @@ cpu_set_decrementer(cpu *processor,
processor->decrementer_local_time = (event_queue_time(processor->events)
+ decrementer);
if (decrementer < 0 && old_decrementer >= 0)
- /* A decrementer interrupt occures if the sign of the decrement
+ /* A decrementer interrupt occurs if the sign of the decrement
register is changed from positive to negative by the load
instruction */
decrementer_interrupt(processor);
@@ -137,7 +137,7 @@ INLINE_CPU\
#if WITH_IDECODE_CACHE_SIZE
-/* Return the cache entry that matches the given CIA. No guarentee
+/* Return the cache entry that matches the given CIA. No guarantee
that the cache entry actually contains the instruction for that
address */
@@ -158,7 +158,7 @@ INLINE_CPU\
inner vm maps, to have the cpu its self provide memory manipulation
functions. (eg cpu_instruction_fetch() cpu_data_read_4())
- Unfortunatly in addition to these functions is the need (for the
+ Unfortunately in addition to these functions is the need (for the
debugger) to be able to read/write to memory in ways that violate
the vm protection (eg store breakpoint instruction in the
instruction map). */
@@ -204,7 +204,7 @@ INLINE_CPU\
/* Registers:
This model exploits the PowerPC's requirement for a synchronization
- to occure after (or before) the update of any context controlling
+ to occurs after (or before) the update of any context controlling
register. All context sync points must call the sync function
below to when ever a synchronization point is reached */
@@ -430,7 +430,7 @@ INLINE_DEVICE\
disks file system. The operations would be implemented using the
basic block I/O model provided by the disk.
- This model includes methods that faciliate the creation of device
+ This model includes methods that facilitate the creation of device
instance and (should a given device support it) standard operations
on those instances.
@@ -514,10 +514,10 @@ INLINE_DEVICE\
cpu *processor,
unsigned_word cia);
-/* This interrupt event will then be propogated to any attached
+/* This interrupt event will then be propagated to any attached
interrupt destinations.
- Any interpretation of PORT and VALUE is model dependant. However
+ Any interpretation of PORT and VALUE is model dependent. However
as guidelines the following are recommended: PCI interrupts a-d
correspond to lines 0-3; level sensative interrupts be requested
with a value of one and withdrawn with a value of 0; edge sensative
@@ -46,7 +46,7 @@
/* EMULATION
- BUG - Motorola's embeded firmware BUG interface
+ BUG - Motorola's embedded firmware BUG interface
DESCRIPTION
@@ -71,7 +71,7 @@
#define _NETWR 0x019 /* Write to host */
#define _NETCFIG 0x01a /* Configure network parameters */
#define _NETOPN 0x01b /* Open file for reading */
-#define _NETFRD 0x01c /* Retreive specified file blocks */
+#define _NETFRD 0x01c /* Retrieve specified file blocks */
#define _NETCTRL 0x01d /* Implement special control functions */
#define _OUTCHR 0x020 /* Output character (pointer / pointer format) */
#define _OUTSTR 0x021 /* Output string (pointer / pointer format) */
@@ -46,7 +46,7 @@
instruction. By doing this, emul_chirp is able to catch and handle
any invalid data accesses it makes while emulating a client call.
- When such an exception occures, emul_chirp is able to recover by
+ When such an exception occurs, emul_chirp is able to recover by
restoring the processor and then calling the clients callback
interface so that the client can recover from the data exception.
@@ -160,7 +160,7 @@ struct _os_emul_data {
/* Emulation of simple UNIX system calls that are common on all systems. */
-/* Structures that are common agmonst the UNIX varients */
+/* Structures that are common among the UNIX variants */
struct unix_timeval {
signed32 tv_sec; /* seconds */
signed32 tv_usec; /* microseconds */
@@ -37,7 +37,7 @@
variables.
TIME_OF_EVENT: this holds the time at which the next event is ment
- to occure. If no next event it will hold the time of the last
+ to occur. If no next event it will hold the time of the last
event.
TIME_FROM_EVENT: The current distance from TIME_OF_EVENT. If an
@@ -195,7 +195,7 @@ insert_event_entry(event_queue *events,
if (delta < 0)
error("what is past is past!\n");
- /* compute when the event should occure */
+ /* compute when the event should occur */
time_of_event = event_queue_time(events) + delta;
/* find the queue insertion point - things are time ordered */
@@ -99,7 +99,7 @@ print_icache_extraction(lf *file,
/* Define a storage area for the cache element */
if (what_to_declare == undef_variables) {
- /* We've finished with the value - destory it */
+ /* We've finished with the value - destroy it */
lf_indent_suppress(file);
lf_printf(file, "#undef %s\n", entry_name);
return;
@@ -478,8 +478,8 @@ print_icache_struct(insn_table *instructions,
lf_printf(file, "} idecode_cache;\n");
}
else {
- /* alernativly, since no cache, emit a dummy definition for
- idecode_cache so that code refering to the type can still compile */
+ /* alernatively, since no cache, emit a dummy definition for
+ idecode_cache so that code referring to the type can still compile */
lf_printf(file, "typedef void idecode_cache;\n");
}
lf_printf(file, "\n");
@@ -596,7 +596,7 @@ idecode_declare_if_switch(insn_table *table,
&& table->parent->opcode_rule->gen == array_gen) {
print_idecode_switch_function_header(file,
table,
- 0/*isnt function definition*/);
+ 0/* isn't function definition */);
}
}
@@ -691,7 +691,7 @@ print_run_until_stop_body(lf *file,
{
/* Output the function to execute real code:
- Unfortunatly, there are multiple cases to consider vis:
+ Unfortunately, there are multiple cases to consider vis:
<icache> X <smp> X <events> X <keep-running-flag> X ...
@@ -1422,7 +1422,7 @@ print_idecode_validate(lf *file,
proper.
The PowerPC spec requires a CSI after MSR[FP] is changed and when
- ever a CSI occures we flush the instruction cache. */
+ ever a CSI occurs we flush the instruction cache. */
{
if (it_is("f", instruction->file_entry->fields[insn_flags])) {
@@ -32,9 +32,9 @@
o cached - separate cracker and semantic
- Two independant functions are created. Firstly the
+ Two independent functions are created. Firstly the
function that cracks an instruction entering it into a
- cache and secondly the semantic function propper that
+ cache and secondly the semantic function proper that
uses the cache.
o cached - semantic + cracking semantic
@@ -45,7 +45,7 @@
cracker and the semantic function when there is a
cache miss).
- For each of these general forms, several refinements can occure:
+ For each of these general forms, several refinements can occur:
o do/don't duplicate/expand semantic functions
@@ -118,7 +118,7 @@ hw_cpu_init_address(device *me)
/* Take the interrupt and synchronize its delivery with the clock. If
we've not yet scheduled an interrupt for the next clock tick, take
- the oportunity to do it now */
+ the opportunity to do it now */
static void
hw_cpu_interrupt_event(device *me,
@@ -35,7 +35,7 @@
/* DEVICE
- eeprom - JEDEC? compatible electricaly erasable programable device
+ eeprom - JEDEC? compatible electricaly erasable programmable device
DESCRIPTION
@@ -43,7 +43,7 @@
This device implements a small byte addressable EEPROM.
Programming is performed using the same write sequences as used by
- standard modern EEPROM components. Writes occure in real time, the
+ standard modern EEPROM components. Writes occur in real time, the
device returning a progress value until the programing has been
completed.
@@ -55,10 +55,10 @@
<<glue>>: In addition to driving its output interrupt port with any
value written to an interrupt input port is stored in the
corresponding <<output>> register. Such input interrupts, however,
- are not propogated to an output interrupt port.
+ are not propagated to an output interrupt port.
<<glue-and>>: The bit-wise AND of the interrupt inputs is computed
- and then both stored in <<output>> register zero and propogated to
+ and then both stored in <<output>> register zero and propagated to
output interrupt output port zero.
@@ -37,7 +37,7 @@
This device models the primary/secondary <<ide>> controller
described in the [CHRPIO] document.
- The controller has separate independant interrupt outputs for each
+ The controller has separate independent interrupt outputs for each
<<ide>> bus.
@@ -91,7 +91,7 @@
| i0,0,1c,6 1 \
| i0,0,20,0 8' \
- Note: the fouth and fifth reg entries specify that the register is
+ Note: the fourth and fifth reg entries specify that the register is
at an offset into the address specified by the base register
(<<assigned-addresses>>); Apart from restrictions placed by the
<<pci>> specification, no restrictions are placed on the number of
@@ -508,7 +508,7 @@ get_status(device *me,
}
-/* The address presented to the IDE controler is decoded and then
+/* The address presented to the IDE controller is decoded and then
mapped onto a controller:reg pair */
enum {
@@ -182,7 +182,7 @@ static device_callbacks const hw_file_callbacks = {
eeprom requires a complex sequence of accesses). The
<<real-address>> is specified as <<0x0c00>> which is the offset
into the eeprom. For brevity, most of the eeprom properties have
- been omited.
+ been omitted.
| /iobus/eeprom@0xfff00000/reg 0xfff00000 0x80000
| /openprom/init/data@0xfff00c00/real-address 0x0c00
@@ -576,7 +576,7 @@ create_ppc_elf_stack_frame(device *me,
const unsigned sizeof_argv = sizeof_arguments(argv);
const unsigned_word start_argv = start_envp - sizeof_argv;
- /* link register save address - alligned to a 16byte boundary */
+ /* link register save address - aligned to a 16byte boundary */
const unsigned_word top_of_stack = ((start_argv
- 2 * sizeof(unsigned_word))
& ~0xf);
@@ -883,7 +883,7 @@ do_end_of_interrupt_register_N_write(device *me,
DTRACE(opic, ("eoi %d - ignoring nonzero value\n", dest->nr));
}
- /* user doing wierd things? */
+ /* user doing weird things? */
if (dest->current_in_service == NULL) {
DTRACE(opic, ("eoi %d - strange, no current interrupt\n", dest->nr));
return;
@@ -54,7 +54,7 @@
DESCRIPTION
- Typical hardware dependant hack. This device allows the firmware
+ Typical hardware dependent hack. This device allows the firmware
to gain access to all the things the firmware needs (but the OS
doesn't).
@@ -65,7 +65,7 @@
Define a number of mappings from the parent bus to one of this
devices PCI busses. The exact format of the <<parent-phys-addr>>
- is parent bus dependant. The format of <<my-phys-addr>> is
+ is parent bus dependent. The format of <<my-phys-addr>> is
described in the Open Firmware PCI bindings document (note that the
address must be non-relocatable).
@@ -93,7 +93,7 @@
Since device tree entries that are specified on the command line
are added before most of the device tree has been built it is often
- necessary to explictly add certain device properties and thus
+ necessary to explicitly add certain device properties and thus
ensure they are already present in the device tree. For the
<<phb>> one such property is parent busses <<#address-cells>>.
@@ -157,7 +157,7 @@
The Open Firmware PCI bus bindings document (rev 1.6) suggests that
the register field of non-relocatable PCI address should be zero.
- Unfortunatly, PCI addresses specified in the <<assigned-addresses>>
+ Unfortunately, PCI addresses specified in the <<assigned-addresses>>
property must be both non-relocatable and have non-zero register
fields.
@@ -319,7 +319,7 @@ hw_phb_attach_address(device *me,
&& type != hw_phb_subtractive_decode)
device_error(me, "attach type (%d) specified by %s invalid",
type, device_path(client));
- /* attach it to the relevent bus */
+ /* attach it to the relevant bus */
DTRACE(phb, ("attach %s - %s %s:0x%lx (0x%lx bytes)\n",
device_path(client),
hw_phb_decode_name(type),
@@ -32,7 +32,7 @@
The properties of this device are used, during initialization, to
specify the value various simulation trace options. The
- initialization can occure implicitly (during device tree init) or
+ initialization can occur implicitly (during device tree init) or
explicitly using this devices ioctl method.
The actual options and their default values (for a given target)
@@ -46,7 +46,7 @@
/* 64bit target expressions:
- Unfortunatly 128bit arrithemetic isn't that common. Consequently
+ Unfortunately, 128bit arithmetics isn't that common. Consequently
the 32/64 bit trick can not be used. Instead all calculations are
required to retain carry/overflow information in separate
variables. Even with this restriction it is still possible for the
@@ -41,7 +41,7 @@ typedef enum {
generate_calls = 0x100,
- /* In addition, when refering to fields access them directly instead
+ /* In addition, when referring to fields access them directly instead
of via variables */
generate_calls_with_direct_access
@@ -116,7 +116,7 @@ extern int icache_size;
/* Instruction expansion?
- Should the semantic code for each instruction, when the oportunity
+ Should the semantic code for each instruction, when the opportunity
arrises, be expanded according to the variable opcode files that
the instruction decode process renders constant */
@@ -31,9 +31,9 @@
Interrupts that must immediately force either an abort or restart
of a current instruction are implemented by forcing an instruction
restart. (or to put it another way, long jump). In looking at the
- code it may occure to you that, for some interrupts, they could
+ code it may occur to you that, for some interrupts, they could
return instead of restarting the cpu (eg system_call). While true
- (it once was like that) I've decided to make the behavour of all
+ (it once was like that) I've decided to make the behaviour of all
interrupt routines roughly identical.
Because, a cpu's recorded state (ie what is in the cpu structure)
@@ -52,7 +52,7 @@
If an instruction field was found, enlarge the field size so that
it is forced to at least include bits starting from <force_first>
- (<force_last>). To stop this occuring, use <force_first> = <last>
+ (<force_last>). To stop this occurring, use <force_first> = <last>
+ 1 and <force_last> = <first> - 1.
<force_slash>
@@ -64,7 +64,7 @@
Treat any contained register (string) fields as constant when
determining the instruction field. For the instruction decode (and
- controled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
+ controlled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
what would otherwize be non constant bits of an instruction.
<use_switch>
@@ -252,7 +252,7 @@ zalloc(long size)
return memory;
}
-/* When a CNTRL-C occures, queue an event to shut down the simulation */
+/* When a CNTRL-C occurs, queue an event to shut down the simulation */
static RETSIGTYPE
cntrl_c(int sig)
@@ -35,7 +35,7 @@ INLINE_OS_EMUL\
/* System-call emulation - for user code. Instead of trapping system
- calls to kernel mode, the simulator emulates the kernels behavour */
+ calls to kernel mode, the simulator emulates the kernels behaviour */
INLINE_OS_EMUL\
(void) os_emul_system_call
@@ -47,7 +47,7 @@ INLINE_OS_EMUL\
instructions are added to the instruction table that when executed
call this emulation function. The instruction call emulator should
verify the address that the instruction appears before emulating
- the required behavour. If the verification fails, a zero value
+ the required behaviour. If the verification fails, a zero value
should be returned (indicating instruction illegal). */
INLINE_OS_EMUL\
@@ -390,7 +390,7 @@ psim_options(device *root,
argp += 1;
}
/* force the trace node to process its options now *before* the tree
- initialization occures */
+ initialization occurs */
device_ioctl(tree_find_device(root, "/openprom/trace"),
NULL, 0,
device_ioctl_set_trace);
@@ -990,7 +990,7 @@ psim_write_register(psim *system,
processor = system->processors[which_cpu];
- /* If the data is comming in raw (target order), need to cook it
+ /* If the data is coming in raw (target order), need to cook it
into host order before putting it into PSIM's internal structures */
if (mode == raw_transfer) {
switch (description.size) {
@@ -60,7 +60,7 @@ INLINE_PSIM_ENDIAN(unsigned_4) endian_le2h_4(unsigned_4 x);
INLINE_PSIM_ENDIAN(unsigned_8) endian_le2h_8(unsigned_8 x);
-/* Host dependant:
+/* Host dependent:
The CPP below defines information about the compilation host. In
particular it defines the macro's:
@@ -18,7 +18,7 @@
*/
-#include <signal.h> /* FIXME - should be machine dependant version */
+#include <signal.h> /* FIXME - should be machine dependent version */
#include <stdarg.h>
#include <ctype.h>
@@ -102,7 +102,7 @@ extern int current_target_byte_order;
expect to see (VEA includes things like coherency and the time
base) while OEA is what an operating system expects to see. By
setting these to specific values, the build process is able to
- eliminate non relevent environment code
+ eliminate non relevant environment code
CURRENT_ENVIRONMENT specifies which of vea or oea is required for
the current runtime. */
@@ -126,7 +126,7 @@ extern int current_environment;
/* Events. Devices modeling real H/W need to be able to efficiently
schedule things to do at known times in the future. The event
- queue implements this. Unfortunatly this adds the need to check
+ queue implements this. Unfortunately this adds the need to check
for any events once each full instruction cycle. */
#define WITH_EVENTS (WITH_ENVIRONMENT != USER_ENVIRONMENT)
@@ -182,7 +182,7 @@ extern int current_environment;
This model. Instead allows both little and big endian modes to
either take exceptions or handle miss aligned transfers.
- If 0 is specified then for big-endian mode miss alligned accesses
+ If 0 is specified then for big-endian mode miss aligned accesses
are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the
processor will fault on them (STRICT_ALIGNMENT). */
@@ -285,7 +285,7 @@ extern int current_stdio;
speed improvement (x3-x5). In the case of RISC (sparc) while the
performance gain isn't as great it is still significant.
- Each module is controled by the macro <module>_INLINE which can
+ Each module is controlled by the macro <module>_INLINE which can
have the values described below
0 Do not inline any thing for the given module
@@ -385,7 +385,7 @@ extern int current_stdio;
Prefix to any declaration of a global object (function or
variable) that should not be inlined and should have only one
definition. The #ifndef wrapper goes around the definition
- propper to ensure that only one copy is generated.
+ proper to ensure that only one copy is generated.
nb: this will not work when a module is being inlined for every
use.
@@ -494,7 +494,7 @@ extern int current_stdio;
#define MON_INLINE (DEFAULT_INLINE ? ALL_INLINE : 0)
#endif
-/* Code called on the rare occasions that an interrupt occures. */
+/* Code called on the rare occasions that an interrupt occurs. */
#ifndef INTERRUPTS_INLINE
#define INTERRUPTS_INLINE DEFAULT_INLINE
@@ -454,7 +454,7 @@ count_entries(device *current,
-/* parse: <address> ::= <token> ; device dependant */
+/* parse: <address> ::= <token> ; device dependent */
STATIC_INLINE_TREE\
(const char *)
@@ -1230,7 +1230,7 @@ tree_find_device(device *root,
/* parse the path */
split_device_specifier(root, path_to_device, &spec);
if (spec.value != NULL)
- return NULL; /* something wierd */
+ return NULL; /* something weird */
/* now find it */
node = split_find_device(root, &spec);
@@ -35,7 +35,7 @@
This function accepts a printf style formatted string as the
argument that describes the entry. Any properties or interrupt
connections added to a device tree using this function are marked
- as having a permenant disposition. When the tree is (re)
+ as having a permanent disposition. When the tree is (re)
initialized they will be restored to their initial value.
*/
@@ -129,7 +129,7 @@ INLINE_TREE\
Once a device tree has been created the <<device_tree_init()>>
function is used to initialize it. The exact sequence of events
- that occure during initialization are described separatly.
+ that occur during initialization is described separately.
*/
@@ -444,7 +444,7 @@ om_write_word(om_map *map,
}
-/* Bring things into existance */
+/* Bring things into existence */
INLINE_VM\
(vm *)
@@ -59,8 +59,8 @@ INLINE_VM\
unsigned_word cia);
-/* generic block transfers. Dependant on the presence of the
- PROCESSOR arg, either returns the number of bytes transfered or (if
+/* generic block transfers. Dependent on the presence of the
+ PROCESSOR arg, either returns the number of bytes transferred or (if
PROCESSOR is non NULL) aborts the simulation */
INLINE_VM\
@@ -158,7 +158,7 @@ static int maskl = 0;
/* Alternate bank of registers r0-r7 */
-/* Note: code controling SR handles flips between BANK0 and BANK1 */
+/* Note: code controlling SR handles flips between BANK0 and BANK1 */
#define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
#define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
@@ -738,7 +738,7 @@ static int nsamples;
#define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
#define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
-#define SCI_RDRF 0x40 /* Recieve data register full */
+#define SCI_RDRF 0x40 /* Receive data register full */
#define SCI_TDRE 0x80 /* Transmit data register empty */
static int
@@ -1269,7 +1269,7 @@ macl (int *regs, unsigned char *memory, int n, int m)
mach |= 0xffff8000; /* Sign extend higher 16 bits */
}
else
- mach = mach & 0x00007fff; /* Postive Result */
+ mach = mach & 0x00007fff; /* Positive Result */
}
MACL = macl;
@@ -40,7 +40,7 @@ typedef union
out-of-bounds accesses of sregs.i . This wart of the code could be
fixed by making fregs part of sregs, and including pc too - to avoid
alignment repercussions - but this would cause very onerous union /
- structure nesting, which would only be managable with anonymous
+ structure nesting, which would only be manageable with anonymous
unions and structs. */
union
{
@@ -35,7 +35,7 @@ typedef struct _v850_regs {
reg_t mpu0_sregs[28]; /* mpu0 system registers */
reg_t mpu1_sregs[28]; /* mpu1 system registers */
reg_t fpu_sregs[28]; /* fpu system registers */
- reg_t selID_sregs[7][32]; /* system registers, selID 1 thru selID 7 */
+ reg_t selID_sregs[7][32]; /* system registers, selID 1 through selID 7 */
reg64_t vregs[32]; /* vector registers. */
} v850_regs;
@@ -360,7 +360,7 @@ Multiply64 (int sign, unsigned long op0)
hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
/* We now need to add all of these results together, taking care
- to propogate the carries from the additions: */
+ to propagate the carries from the additions: */
RdLo = Add32 (lo, (mid1 << 16), & carry);
RdHi = carry;
RdLo = Add32 (RdLo, (mid2 << 16), & carry);