[16/24] Pick msa target when appropriate and put msa registers into vector reggroups.
Commit Message
gdb/ChangeLog:
* mips-linux-nat.c: Include "features/mips-msa-linux.c" and
"features/mips64-msa-linux.c".
(mips_linux_read_description): New "have_msa" variable which is
set using ptrace result and return appropriate target based on
"have_msa".
(initialize_tdesc_mips_msa_linux,
initialize_tdesc_mips64_msa_linux): Initilizer functions for MSA
targets.
*mips-tdep.c (mips_register_reggroup_p): Put msa registers into
vector reggroup.
---
gdb/mips-linux-nat.c | 35 +++++++++++++++++++++++++++++++++--
gdb/mips-tdep.c | 4 +++-
2 files changed, 36 insertions(+), 3 deletions(-)
@@ -42,8 +42,10 @@
#include "features/mips-dsp-linux.c"
#include "features/mips-fpu64-linux.c"
#include "features/mips-fpu64-dsp-linux.c"
+#include "features/mips-msa-linux.c"
#include "features/mips64-linux.c"
#include "features/mips64-dsp-linux.c"
+#include "features/mips64-msa-linux.c"
#ifndef PTRACE_GET_THREAD_AREA
#define PTRACE_GET_THREAD_AREA 25
@@ -611,6 +613,7 @@ mips_linux_read_description (struct target_ops *ops)
static int have_dsp = -1;
static int have_fpu64 = -1;
+ static int have_msa = -1;
if (have_fpu64 < 0)
{
@@ -631,12 +634,36 @@ mips_linux_read_description (struct target_ops *ops)
break;
case EIO:
have_fpu64 = 0;
+ have_msa = 0;
break;
default:
perror_with_name ("ptrace");
break;
}
}
+
+ /* Check for MSA, which requires FR=1 */
+ if (have_msa < 0)
+ {
+ int tid;
+ int res;
+ uint32_t regs[32*4 + 8];
+ struct iovec iov;
+
+ tid = ptid_get_lwp (inferior_ptid);
+ if (tid == 0)
+ tid = ptid_get_pid (inferior_ptid);
+
+ /* this'd probably be better */
+ //have_msa = (getauxval(AT_HWCAP) & 0x2) != 0;
+
+ /* Test MSAIR */
+ iov.iov_base = regs;
+ iov.iov_len = sizeof(regs);
+ res = ptrace (PTRACE_GETREGSET, tid, NT_MIPS_MSA, &iov);
+ have_msa = (res >= 0) && regs[32*4 + 0];
+ }
+
if (have_dsp < 0)
{
int tid;
@@ -664,9 +691,11 @@ mips_linux_read_description (struct target_ops *ops)
/* Report that target registers are a size we know for sure
that we can get from ptrace. */
if (_MIPS_SIM == _ABIO32)
- return tdescs[have_dsp][have_fpu64];
+ return have_msa ? tdesc_mips_msa_linux
+ : tdescs[have_dsp][have_fpu64];
else
- return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
+ return have_msa ? tdesc_mips64_msa_linux :
+ have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
}
/* -1 if the kernel and/or CPU do not support watch registers.
@@ -1023,6 +1052,8 @@ triggers a breakpoint or watchpoint."),
initialize_tdesc_mips_dsp_linux ();
initialize_tdesc_mips_fpu64_linux ();
initialize_tdesc_mips_fpu64_dsp_linux ();
+ initialize_tdesc_mips_msa_linux ();
initialize_tdesc_mips64_linux ();
initialize_tdesc_mips64_dsp_linux ();
+ initialize_tdesc_mips64_msa_linux ();
}
@@ -776,7 +776,9 @@ mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
int pseudo = regnum / gdbarch_num_regs (gdbarch);
if (reggroup == all_reggroup)
return pseudo;
- vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
+ vector_p = (TYPE_VECTOR (register_type (gdbarch, regnum)) ||
+ rawnum == mips_regnum (gdbarch)->msa_csr ||
+ rawnum == mips_regnum (gdbarch)->msa_ir);
float_p = (mips_float_register_p (gdbarch, rawnum) ||
rawnum == mips_regnum (gdbarch)->fp_control_status ||
rawnum == mips_regnum (gdbarch)->fp_implementation_revision);