[ARM] Clear reserved bits in CPSR
Commit Message
Pedro Alves <palves@redhat.com> writes:
> No comments on the ARM specifics, but I think it's clearer to write
> this as:
>
> regs[ARM_CPSR_GREGNUM] &= 0xff0fffff;
Fixed. Patch is pushed in.
@@ -1,3 +1,8 @@
+2016-04-22 Yao Qi <yao.qi@linaro.org>
+
+ * aarch32-linux-nat.c (aarch32_gp_regcache_supply): Clear CPSR
+ bits 20 to 23.
+
2016-04-22 Joel Brobecker <brobecker@adacore.com>
* MAINTAINER: Remove myself as AIX Maintainer.
@@ -37,7 +37,11 @@ aarch32_gp_regcache_supply (struct regcache *regcache, uint32_t *regs,
regcache_raw_supply (regcache, regno, ®s[regno]);
if (arm_apcs_32)
- regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]);
+ {
+ /* Clear reserved bits bit 20 to bit 23. */
+ regs[ARM_CPSR_GREGNUM] &= 0xff0fffff;
+ regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]);
+ }
else
regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_PC_REGNUM]);
@@ -1,5 +1,10 @@
2016-04-22 Yao Qi <yao.qi@linaro.org>
+ * linux-aarch32-low.c (arm_store_gregset): Clear CPSR bits 20
+ to 23.
+
+2016-04-22 Yao Qi <yao.qi@linaro.org>
+
* linux-low.c (lwp_signal_can_be_delivered): Don't deliver
signal when stepping over breakpoint with software single
step.
@@ -77,6 +77,7 @@ arm_store_gregset (struct regcache *regcache, const void *buf)
int i;
char zerobuf[8];
const uint32_t *regs = (const uint32_t *) buf;
+ uint32_t cpsr = regs[ARM_CPSR_GREGNUM];
memset (zerobuf, 0, 8);
for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++)
@@ -85,7 +86,9 @@ arm_store_gregset (struct regcache *regcache, const void *buf)
for (; i < ARM_PS_REGNUM; i++)
supply_register (regcache, i, zerobuf);
- supply_register (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]);
+ /* Clear reserved bits bit 20 to bit 23. */
+ cpsr &= 0xff0fffff;
+ supply_register (regcache, ARM_PS_REGNUM, &cpsr);
}
/* Collect NUM number of VFP registers from REGCACHE to buffer BUF. */