gdb/riscv: Add target description support

  This is a slightly revised version of the RISC-V target descriptions
patch.

Changes since the first version:

  - Fixed bug spotted by Jim in gdb/configure.tgt

  - Correctly generated the gdb/features/riscv/{32,64}bit-csr.c files.

  - Greatly simplified riscv_register_types function, we now only
    override a few specific cases, as a result the quad FP union type
    has been removed.  I would expect this to be handled through
    target descriptions as/when we add quad support.

  - Added docs and NEWS entries as suggested by Pedro.

Everything else is unchanged.

I'm proposing to merge this version if everyone is happy with it.

Thanks,
Andrew

--

gdb/riscv: Add target description support

This commit adds target description support for riscv.

I've used the split feature approach for specifying the architectural
features, and the CSR feature is auto-generated from the riscv-opc.h
header file.

If the target doesn't provide a suitable target description then GDB
will build one by looking at the bfd headers.

This commit does not implement target description creation for the
Linux or FreeBSD native targets, both of these will need to add
read_description methods into their respective target classes, which
probe the target features, and then call
riscv_create_target_description to build a suitable target
description.  Until this is done Linux and FreeBSD will get the same
default target description based on the bfd that bare-metal targets
get.

I've only added feature descriptions for 32 and 64 bit registers, 128
bit registers (for RISC-V) are not supported in the reset of GDB yet.

This commit removes the special reading of the MISA register in order
to establish the target features, this was only used for figuring out
the f-register size, and even that wasn't done consistently.  We now
rely on the target to tell us what size of registers it has (or look
in the BFD as a last resort).  The result of this is that we should
now support RV64 targets with 32-bit float, though I have not
extensively tested this combination yet.

	* Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o.
	(HFILES_NO_SRCDIR): Add arch/riscv.h.
	* arch/riscv.c: New file.
	* arch/riscv.h: New file.
	* configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into
	this list, and add arch/riscv.o.
	* features/Makefile: Add riscv features.
	* features/riscv/32bit-cpu.c: New file.
	* features/riscv/32bit-cpu.xml: New file.
	* features/riscv/32bit-csr.c: New file.
	* features/riscv/32bit-csr.xml: New file.
	* features/riscv/32bit-fpu.c: New file.
	* features/riscv/32bit-fpu.xml: New file.
	* features/riscv/64bit-cpu.c: New file.
	* features/riscv/64bit-cpu.xml: New file.
	* features/riscv/64bit-csr.c: New file.
	* features/riscv/64bit-csr.xml: New file.
	* features/riscv/64bit-fpu.c: New file.
	* features/riscv/64bit-fpu.xml: New file.
	* features/riscv/rebuild-csr-xml.sh: New file.
	* riscv-tdep.c: Add 'arch/riscv.h' include.
	(riscv_gdb_reg_names): Delete.
	(csr_reggroup): New global.
	(struct riscv_register_alias): Delete.
	(struct riscv_register_feature): New structure.
	(riscv_register_aliases): Delete.
	(riscv_xreg_feature): New global.
	(riscv_freg_feature): New global.
	(riscv_virtual_feature): New global.
	(riscv_csr_feature): New global.
	(riscv_create_csr_aliases): New function.
	(riscv_read_misa_reg): Delete.
	(riscv_has_feature): Delete.
	(riscv_isa_xlen): Simplify, just return cached xlen.
	(riscv_isa_flen): Simplify, just return cached flen.
	(riscv_has_fp_abi): Update for changes in struct gdbarch_tdep.
	(riscv_register_name): Update to make use of tdesc_register_name.
	Look up xreg and freg names in the new globals riscv_xreg_feature
	and riscv_freg_feature.  Don't supply csr aliases here.
	(riscv_fpreg_q_type): Delete.
	(riscv_register_type): Use tdesc_register_type in almost all
	cases, override the returned type in a few specific cases only.
	(riscv_print_one_register_info): Handle errors reading registers.
	(riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for
	registers that are otherwise unknown to GDB.  Also check the
	csr_reggroup.
	(riscv_print_registers_info): Remove assert about upper register
	number, and use gdbarch_register_reggroup_p instead of
	short-cutting.
	(riscv_find_default_target_description): New function.
	(riscv_check_tdesc_feature): New function.
	(riscv_add_reggroups): New function.
	(riscv_setup_register_aliases): New function.
	(riscv_init_reggroups): New function.
	(_initialize_riscv_tdep): Add calls to setup CSR aliases, and
	setup register groups.  Register new riscv debug variable.
	* riscv-tdep.h: Add 'arch/riscv.h' include.
	(struct gdbarch_tdep): Remove abi union, and add
	riscv_gdbarch_features field.  Remove cached quad floating point
	type, and provide initialisation for double type field.
	* target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to
	the list of targets using the feature based target descriptions.
	* NEWS: Mention target description support.

gdb/doc/ChangeLog:

	* gdb.texinfo (Standard Target Features): Add RISC-V Features
	sub-section.
---
 gdb/ChangeLog                         |  66 +++
 gdb/Makefile.in                       |   2 +
 gdb/NEWS                              |   2 +
 gdb/arch/riscv.c                      |  69 +++
 gdb/arch/riscv.h                      |  64 +++
 gdb/configure.tgt                     |   9 +-
 gdb/doc/ChangeLog                     |   5 +
 gdb/doc/gdb.texinfo                   |  36 ++
 gdb/features/Makefile                 |  11 +
 gdb/features/riscv/32bit-cpu.c        |  46 ++
 gdb/features/riscv/32bit-cpu.xml      |  43 ++
 gdb/features/riscv/32bit-csr.c        | 253 ++++++++++
 gdb/features/riscv/32bit-csr.xml      | 250 ++++++++++
 gdb/features/riscv/32bit-fpu.c        |  48 ++
 gdb/features/riscv/32bit-fpu.xml      |  46 ++
 gdb/features/riscv/64bit-cpu.c        |  46 ++
 gdb/features/riscv/64bit-cpu.xml      |  43 ++
 gdb/features/riscv/64bit-csr.c        | 253 ++++++++++
 gdb/features/riscv/64bit-csr.xml      | 250 ++++++++++
 gdb/features/riscv/64bit-fpu.c        |  56 +++
 gdb/features/riscv/64bit-fpu.xml      |  52 ++
 gdb/features/riscv/rebuild-csr-xml.sh |  29 ++
 gdb/riscv-tdep.c                      | 888 ++++++++++++++++++++--------------
 gdb/riscv-tdep.h                      |  29 +-
 gdb/target-descriptions.c             |   1 +
 25 files changed, 2220 insertions(+), 377 deletions(-)
 create mode 100644 gdb/arch/riscv.c
 create mode 100644 gdb/arch/riscv.h
 create mode 100644 gdb/features/riscv/32bit-cpu.c
 create mode 100644 gdb/features/riscv/32bit-cpu.xml
 create mode 100644 gdb/features/riscv/32bit-csr.c
 create mode 100644 gdb/features/riscv/32bit-csr.xml
 create mode 100644 gdb/features/riscv/32bit-fpu.c
 create mode 100644 gdb/features/riscv/32bit-fpu.xml
 create mode 100644 gdb/features/riscv/64bit-cpu.c
 create mode 100644 gdb/features/riscv/64bit-cpu.xml
 create mode 100644 gdb/features/riscv/64bit-csr.c
 create mode 100644 gdb/features/riscv/64bit-csr.xml
 create mode 100644 gdb/features/riscv/64bit-fpu.c
 create mode 100644 gdb/features/riscv/64bit-fpu.xml
 create mode 100755 gdb/features/riscv/rebuild-csr-xml.sh

gdb/riscv: Add target description support

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