V6 [PATCH] x86: Add <sys/platform/x86.h>
Commit Message
On 10/24/18, Florian Weimer <fweimer@redhat.com> wrote:
> * H. J. Lu:
>
>> On 10/24/18, Florian Weimer <fweimer@redhat.com> wrote:
>>> * H. J. Lu:
>>>
>>>> On 10/24/18, Florian Weimer <fweimer@redhat.com> wrote:
>>>>> * H. J. Lu:
>>>>>
>>>>>> +@defmac HAS_CPU_FEATURE(name)
>>>>>> +
>>>>>> +Evaluate to true if the CPU feature @code{name} is supported as
>>>>>> indicated
>>>>>> +by @code{CPUID} instruction. The available features are:
>>>>>
>>>>> I'm still puzzled why we expose this function. It will only confuse
>>>>> programmers.
>>>>
>>>> A use case: AVX512 bits can be used to tell Xeon Phi from Skylake
>>>> sever even if AVX512 instructions aren't used/needed at all.
>>>
>>> Do you mean checking fore AVX512ER? Would you consider this good
>>> practice?
>>>
>>> It is actually future-proof? What if Skylake successors implement
>>> AVX512ER? Do you really want applications to select the Xeon Phi
>>> workarounds in this case?
>>>
>>> I still think if you care about Xeon Phi, you should use <cpuid.h> from
>>> GCC and make the checks as explicit as possible. The <cpuid.h>
>>> facilities should not be too difficult to use for that purpose.
>>
>> Xeon Phi is an example. There are other cases where one may want to
>> know if a feature exists in CPU, not necessarily wants/needs to use the
>> feature. The main purpose of <sys/platform/x86.h> is to make it easier
>> to check if a feature is usable or exists.
>
> I think this interface should be targeted at discovering features, not
> CPU models, to avoid confusion.
>
> If you need to figure out the model, you really need to look at CPUID
> results. Everything else will be brittle, due to evolving CPU lines and
> virtualization.
Here is the patch with CPU_FEATURE_USABLE only. OK for master
branch?
Comments
* H. J. Lu:
> Here is the patch with CPU_FEATURE_USABLE only. OK for master
> branch?
Thanks. Recently, the matter of special-casing code inside target
clones came up on the glibc list:
<https://gcc.gnu.org/ml/gcc-help/2018-10/msg00118.html>
Do you think it might be possible to eventually turn some results for
CPU_FEATURE_USABLE in target clones into compile-time constants because
the compiler knows the results of the feature selection in the
automatically generated IFUNC resolver?
Thanks,
Florian
On 10/25/18, Florian Weimer <fweimer@redhat.com> wrote:
> * H. J. Lu:
>
>
>> Here is the patch with CPU_FEATURE_USABLE only. OK for master
>> branch?
>
> Thanks. Recently, the matter of special-casing code inside target
> clones came up on the glibc list:
I am going to check it in.
> <https://gcc.gnu.org/ml/gcc-help/2018-10/msg00118.html>
>
> Do you think it might be possible to eventually turn some results for
> CPU_FEATURE_USABLE in target clones into compile-time constants because
> the compiler knows the results of the feature selection in the
> automatically generated IFUNC resolver?
By definition, CPU_FEATURE_USABLE is evaluated at run-time.
Can GCC be extended to allow intrinsics in target_clone.
* H. J. Lu:
> On 10/25/18, Florian Weimer <fweimer@redhat.com> wrote:
>> * H. J. Lu:
>>
>>
>>> Here is the patch with CPU_FEATURE_USABLE only. OK for master
>>> branch?
>>
>> Thanks. Recently, the matter of special-casing code inside target
>> clones came up on the glibc list:
>
> I am going to check it in.
>
>> <https://gcc.gnu.org/ml/gcc-help/2018-10/msg00118.html>
>>
>> Do you think it might be possible to eventually turn some results for
>> CPU_FEATURE_USABLE in target clones into compile-time constants because
>> the compiler knows the results of the feature selection in the
>> automatically generated IFUNC resolver?
>
> By definition, CPU_FEATURE_USABLE is evaluated at run-time.
> Can GCC be extended to allow intrinsics in target_clone.
I am wondering if we can tweak CPU_FEATURE_USABLE in such a way that it
can be easily compatible with future intrinsics.
Thanks,
Florian
* H. J. Lu:
> /* CPU_FEATURE_USABLE evaluates to true if the feature is usable. */
> #define CPU_FEATURE_USABLE(name) \
> ((need_arch_feature_##name \
> && (x86_get_arch_feature (index_arch_##name##_Usable) \
> & (bit_arch_##name##_Usable)) != 0) \
> || (!need_arch_feature_##name \
> && (x86_get_cpuid_registers (index_cpu_##name)->reg_##name \
> & (bit_cpu_##name)) != 0))
I still think this is wrong. This should be a const function, with a
single argument, returning bool, so that we do not expose the internal
implementation. It will also be possible to use this function from Ada,
Fortran, and so on. This is not possible with a preprocessor macro.
Thanks,
Florian
On 10/25/18, Florian Weimer <fweimer@redhat.com> wrote:
> * H. J. Lu:
>
>> /* CPU_FEATURE_USABLE evaluates to true if the feature is usable. */
>> #define CPU_FEATURE_USABLE(name) \
>> ((need_arch_feature_##name \
>> && (x86_get_arch_feature (index_arch_##name##_Usable) \
>> & (bit_arch_##name##_Usable)) != 0) \
>> || (!need_arch_feature_##name \
>> && (x86_get_cpuid_registers (index_cpu_##name)->reg_##name \
>> & (bit_cpu_##name)) != 0))
>
> I still think this is wrong. This should be a const function, with a
> single argument, returning bool, so that we do not expose the internal
The only things exposed are
enum
{
/* The integer bit array index for the first set of internal feature
bits. */
FEATURE_INDEX_1 = 0,
FEATURE_INDEX_2,
/* The current maximum size of the feature integer bit array. */
FEATURE_INDEX_MAX
};
enum
{
COMMON_CPUID_INDEX_1 = 0,
COMMON_CPUID_INDEX_7,
COMMON_CPUID_INDEX_80000001,
/* Keep the following line at the end. */
COMMON_CPUID_INDEX_MAX
};
struct cpuid_registers
{
unsigned int eax;
unsigned int ebx;
unsigned int ecx;
unsigned int edx;
};
following the conventions of C/C++.
> implementation. It will also be possible to use this function from Ada,
> Fortran, and so on. This is not possible with a preprocessor macro.
This is designed for C/C++. This is never intended for Fortran nor
Ada. If there are requests for Fortran or Ada, we can investigate different
approaches for them.
Any other comments?
On Thu, Oct 25, 2018 at 11:11 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On 10/25/18, Florian Weimer <fweimer@redhat.com> wrote:
> > * H. J. Lu:
> >
> >> /* CPU_FEATURE_USABLE evaluates to true if the feature is usable. */
> >> #define CPU_FEATURE_USABLE(name) \
> >> ((need_arch_feature_##name \
> >> && (x86_get_arch_feature (index_arch_##name##_Usable) \
> >> & (bit_arch_##name##_Usable)) != 0) \
> >> || (!need_arch_feature_##name \
> >> && (x86_get_cpuid_registers (index_cpu_##name)->reg_##name \
> >> & (bit_cpu_##name)) != 0))
> >
> > I still think this is wrong. This should be a const function, with a
> > single argument, returning bool, so that we do not expose the internal
>
> The only things exposed are
>
> enum
> {
> /* The integer bit array index for the first set of internal feature
> bits. */
> FEATURE_INDEX_1 = 0,
> FEATURE_INDEX_2,
> /* The current maximum size of the feature integer bit array. */
> FEATURE_INDEX_MAX
> };
>
> enum
> {
> COMMON_CPUID_INDEX_1 = 0,
> COMMON_CPUID_INDEX_7,
> COMMON_CPUID_INDEX_80000001,
> /* Keep the following line at the end. */
> COMMON_CPUID_INDEX_MAX
> };
>
> struct cpuid_registers
> {
> unsigned int eax;
> unsigned int ebx;
> unsigned int ecx;
> unsigned int edx;
> };
>
> following the conventions of C/C++.
>
> > implementation. It will also be possible to use this function from Ada,
> > Fortran, and so on. This is not possible with a preprocessor macro.
>
> This is designed for C/C++. This is never intended for Fortran nor
> Ada. If there are requests for Fortran or Ada, we can investigate different
> approaches for them.
>
> Any other comments?
I'd like to add this C/C++ feature to glibc. If there is no objection, I will
check it in tomorrow.
On Tue, 30 Oct 2018, H.J. Lu wrote:
> I'd like to add this C/C++ feature to glibc. If there is no objection, I will
> check it in tomorrow.
I object: it's clear you don't have consensus for this feature in its
presently proposed form.
On Tue, Oct 30, 2018 at 11:15 AM Joseph Myers <joseph@codesourcery.com> wrote:
>
> On Tue, 30 Oct 2018, H.J. Lu wrote:
>
> > I'd like to add this C/C++ feature to glibc. If there is no objection, I will
> > check it in tomorrow.
>
> I object: it's clear you don't have consensus for this feature in its
> presently proposed form.
>
The only concern so far is this feature is C/C++ only. My understanding
is that it is perfectly OK to have <sys/platform/cpu.h> with C/C++
only features.
Am I correct?
On Tue, Oct 30, 2018 at 11:33 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Tue, Oct 30, 2018 at 11:15 AM Joseph Myers <joseph@codesourcery.com> wrote:
> >
> > On Tue, 30 Oct 2018, H.J. Lu wrote:
> >
> > > I'd like to add this C/C++ feature to glibc. If there is no objection, I will
> > > check it in tomorrow.
> >
> > I object: it's clear you don't have consensus for this feature in its
> > presently proposed form.
> >
>
> The only concern so far is this feature is C/C++ only. My understanding
> is that it is perfectly OK to have <sys/platform/cpu.h> with C/C++
> only features.
> Am I correct?
>
FYI, we are working on a testcase to show spinlock scalability issue on
machines with many cores. It is on hjl/spinlock/master branch at
https://github.com/hjl-tools/glibc/
The testcase uses CPU_FEATURE_USABLE and x86_tsc_to_ns.
On Tue, 30 Oct 2018, H.J. Lu wrote:
> On Tue, Oct 30, 2018 at 11:15 AM Joseph Myers <joseph@codesourcery.com> wrote:
> >
> > On Tue, 30 Oct 2018, H.J. Lu wrote:
> >
> > > I'd like to add this C/C++ feature to glibc. If there is no objection, I will
> > > check it in tomorrow.
> >
> > I object: it's clear you don't have consensus for this feature in its
> > presently proposed form.
>
> The only concern so far is this feature is C/C++ only. My understanding
> is that it is perfectly OK to have <sys/platform/cpu.h> with C/C++
> only features.
> Am I correct?
When we're adding new APIs it's necessary to achieve consensus on what the
API should be - especially if the API is a glibc-specific invention, as
here. Even with a more general consensus on C/C++ only features in such a
header, that wouldn't mean consensus in that regard for this particular
feature. We don't work by allowing a day for objections and then checking
things in; consensus-building on an API design is a slower and more
collaborative process than that. This feature should not be checked in
without someone else having reviewed the whole discussion and the patch
and considered carefully whether consensus has been reached on all issues
and the patch is the proper way of implementing the proper API.
On 10/26/18 1:16 AM, Florian Weimer wrote:
> * H. J. Lu:
>
>> /* CPU_FEATURE_USABLE evaluates to true if the feature is usable. */
>> #define CPU_FEATURE_USABLE(name) \
>> ((need_arch_feature_##name \
>> && (x86_get_arch_feature (index_arch_##name##_Usable) \
>> & (bit_arch_##name##_Usable)) != 0) \
>> || (!need_arch_feature_##name \
>> && (x86_get_cpuid_registers (index_cpu_##name)->reg_##name \
>> & (bit_cpu_##name)) != 0))
>
> I still think this is wrong. This should be a const function, with a
> single argument, returning bool, so that we do not expose the internal
> implementation. It will also be possible to use this function from Ada,
> Fortran, and so on. This is not possible with a preprocessor macro.
I think this is the key sticking point for consensus.
We should iterate over this as a success criteria for that discussion.
This isn't the first objection to macros.
In July I also objected.
https://sourceware.org/ml/libc-alpha/2018-07/msg01067.html
~~~
> /* HAS_* evaluates to true if we may use the feature at runtime. */
> #define HAS_CPU_FEATURE(name) \
> ((__x86_get_cpuid_registers (index_cpu_##name)->reg_##name \
> & (bit_cpu_##name)) != 0)
I don't like these as macros.
I would rather an inline function that does all the work within the function
and returns a result of the appropriate type e.g. boolean.
~~~
Please expand on the benefits of this being a macro.
We need to see these benefits to move from a position
where we have sustained objections to a macro API, to one where
we might object to the macros but understand that they are perhaps
the best compromise given your expanded description.
Is there a serious performance implication?
On Wed, Oct 31, 2018 at 7:38 PM Carlos O'Donell <carlos@redhat.com> wrote:
>
> On 10/26/18 1:16 AM, Florian Weimer wrote:
> > * H. J. Lu:
> >
> >> /* CPU_FEATURE_USABLE evaluates to true if the feature is usable. */
> >> #define CPU_FEATURE_USABLE(name) \
> >> ((need_arch_feature_##name \
> >> && (x86_get_arch_feature (index_arch_##name##_Usable) \
> >> & (bit_arch_##name##_Usable)) != 0) \
> >> || (!need_arch_feature_##name \
> >> && (x86_get_cpuid_registers (index_cpu_##name)->reg_##name \
> >> & (bit_cpu_##name)) != 0))
> >
> > I still think this is wrong. This should be a const function, with a
> > single argument, returning bool, so that we do not expose the internal
> > implementation. It will also be possible to use this function from Ada,
> > Fortran, and so on. This is not possible with a preprocessor macro.
>
> I think this is the key sticking point for consensus.
>
> We should iterate over this as a success criteria for that discussion.
>
> This isn't the first objection to macros.
>
> In July I also objected.
>
> https://sourceware.org/ml/libc-alpha/2018-07/msg01067.html
> ~~~
> > /* HAS_* evaluates to true if we may use the feature at runtime. */
> > #define HAS_CPU_FEATURE(name) \
> > ((__x86_get_cpuid_registers (index_cpu_##name)->reg_##name \
> > & (bit_cpu_##name)) != 0)
>
> I don't like these as macros.
>
> I would rather an inline function that does all the work within the function
> and returns a result of the appropriate type e.g. boolean.
> ~~~
>
> Please expand on the benefits of this being a macro.
>
> We need to see these benefits to move from a position
> where we have sustained objections to a macro API, to one where
> we might object to the macros but understand that they are perhaps
> the best compromise given your expanded description.
>
> Is there a serious performance implication?
>
We have some programs, both inside glibc and outside glibc, which
check CPUID. I'd like to switch them to <sys/platform/x86.h>. This
interface:
enum
{
COMMON_CPUID_INDEX_1 = 0,
COMMON_CPUID_INDEX_7,
COMMON_CPUID_INDEX_80000001,
/* Keep the following line at the end. */
COMMON_CPUID_INDEX_MAX
};
struct cpuid_registers
{
unsigned int eax;
unsigned int ebx;
unsigned int ecx;
unsigned int edx;
};
extern const struct cpuid_registers *x86_get_cpuid_registers
(unsigned int) __attribute__ ((const));
extern unsigned int x86_get_arch_feature (unsigned int)
__attribute__ ((const));
/* CPU_FEATURE_USABLE evaluates to true if the feature is usable. */
#define CPU_FEATURE_USABLE(name) \
((need_arch_feature_##name \
&& (x86_get_arch_feature (index_arch_##name##_Usable) \
& (bit_arch_##name##_Usable)) != 0) \
|| (!need_arch_feature_##name \
&& (x86_get_cpuid_registers (index_cpu_##name)->reg_##name \
& (bit_cpu_##name)) != 0))
makes a couple things possible:
1. Multiple features can be checked with a single function call.
2. CPUID instruction takes EAX and optionally ECX as input, It writes to
EAX, EBX, ECD and EDX. Each CPU feature is determined by CPUID with
specific input values and a bit in EAX, EBX, ECX or EDX.
CPU_FEATURE_USABLE macro generate very decent code. There are many
reserved bits in EAX, EBX, ECX and EDX, which may be changed to new CPU
features for future processors. It is easy to add these features to x86.h
with macros without recompiling glibc.
From 23bc7f6c5b939d0e988c7fb1f1fd3580b06af5c5 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Thu, 26 Jul 2018 03:56:53 -0700
Subject: [PATCH] x86: Add <sys/platform/x86.h>
Add <sys/platform/x86.h> to provide an API to access x86 specific platform
features. It makes raw and derived CPUID information available to
applications so that programmers can avoid complicated steps to retrieve
the same information with CPUID instructions.
enum
{
/* The integer bit array index for the first set of internal feature
bits. */
FEATURE_INDEX_1 = 0,
FEATURE_INDEX_2,
/* The current maximum size of the feature integer bit array. */
FEATURE_INDEX_MAX
};
FEATURE_INDEX_1 is used by the public API and FEATURE_INDEX_2 is for
glibc internal use.
enum
{
COMMON_CPUID_INDEX_1 = 0,
COMMON_CPUID_INDEX_7,
COMMON_CPUID_INDEX_80000001,
/* Keep the following line at the end. */
COMMON_CPUID_INDEX_MAX
};
struct cpuid_registers
{
unsigned int eax;
unsigned int ebx;
unsigned int ecx;
unsigned int edx;
};
extern const struct cpuid_registers *x86_get_cpuid_registers
(unsigned int) __attribute__ ((const));
extern unsigned int x86_get_arch_feature (unsigned int)
__attribute__ ((const));
/* CPU_FEATURE_USABLE evaluates to true if the feature is usable. */
#define CPU_FEATURE_USABLE(name) \
((need_arch_feature_##name \
&& (x86_get_arch_feature (index_arch_##name##_Usable) \
& (bit_arch_##name##_Usable)) != 0) \
|| (!need_arch_feature_##name \
&& (x86_get_cpuid_registers (index_cpu_##name)->reg_##name \
& (bit_cpu_##name)) != 0))
Users can use <sys/platform/x86.h> to detect if a CPU feature is usable
at run-time with "CPU_FEATURE_USABLE (AVX)" which evaluates true if glibc
detects that AVX is usable.
Note: "CPU_FEATURE_USABLE (XXX)" evaluates false if the feature isn't
usable or the run-time glibc, which is older than the compile-time
glibc, doesn't support this feature check.
CPUID instruction takes EAX and optionally ECX as input, It writes to
EAX, EBX, ECD and EDX. Each CPU feature is determined by CPUID with
specific input values and a bit in EAX, EBX, ECX or EDX.
CPU_FEATURE_USABLE macro generate very decent code. There are many
reserved bits in EAX, EBX, ECX and EDX, which may be changed to new CPU
features for future processors. It is easy to add these features to x86.h
with macros without recompiling glibc. All CPU and architecture feature
macros should be tested by sysdeps/x86/tst-x86-platform-1.c.
Backward binary compatibility is provided by:
1. x86_get_cpuid_registers returns a pointer to an element of struct
cpuid_registers cpuid[COMMON_CPUID_INDEX_MAX], the cached output of CPUID.
If cpuid index >= COMMON_CPUID_INDEX_MAX, we return a pointer to struct
cpuid_registers with all zeros. This happens when the run-time glibc
doesn't support the newly added cpuid index.
2. x86_get_arch_feature returns 0 if architecture index >=
FEATURE_INDEX_MAX. This happens when the run-time glibc doesn't support
the newly added feature index.
Applications linked against the new x86_get_cpuid_registers and
x86_get_arch_feature will run with the older libc.so. But new
CPU and architecture features won't be detected by the older libc.so.
Add more CPU features for COMMON_CPUID_INDEX_1, COMMON_CPUID_INDEX_7
and COMMON_CPUID_INDEX_80000001. Update tst-get-cpu-features.c to
test all bit_cpu_XXX and bit_arch_XXX bits.
* NEWS: Mention <sys/platform/x86.h>.
* manual/platform.texi: Add entries for <sys/platform/x86.h>.
* sysdeps/mach/hurd/i386/ld.abilist (GLIBC_2.29): Add
x86_get_arch_feature and x86_get_cpuid_registers.
* sysdeps/unix/sysv/linux/i386/ld.abilist (GLIBC_2.29): Likewise.
* sysdeps/unix/sysv/linux/x86_64/64/ld.abilist (GLIBC_2.29):
Likewise.
* sysdeps/unix/sysv/linux/x86_64/x32/ld.abilist (GLIBC_2.29):
Likewise.
* sysdeps/x86/Makefile (tests): Add tst-x86-platform-1,
tst-x86-platform-1-static, tst-x86-platform-2 and
tst-x86-platform-3.
(tests-static): Add tst-x86-platform-1-static.
(modules-names): Add tst-x86-platform-mod-2 and
tst-x86-platform-mod-3.
($(objpfx)tst-x86-platform-mod-2.so): New.
($(objpfx)tst-x86-platform-2): Likewise.
(LDFLAGS-tst-x86-platform-mod-3.so): Likewise.
($(objpfx)tst-x86-platform-mod-3.so): Likewise.
($(objpfx)tst-x86-platform-3): Likewise.
(sysdep_headers): Add sys/platform/x86.h.
* sysdeps/x86/Versions (ld): Add x86_get_cpuid_registers and
x86_get_arch_feature to GLIBC_2.29.
* sysdeps/x86/cpu-features.c (init_cpu_features): Use
_Static_assert on index_arch_Fast_Unaligned_Load.
__get_cpuid_registers and __get_arch_feature.
* sysdeps/x86/cpu-features.h: Include <sys/platform/x86.h>.
(FEATURE_INDEX_1): Removed.
(FEATURE_INDEX_MAX): Likewise.
(COMMON_CPUID_INDEX_XXX): Likewise.
(cpuid_registers): Likewise.
(bit_arch_XXX): Move most to <sys/platform/x86.h>.
(bit_cpu_XXX): Likewise.
(index_cpu_XXX): Likewise.
(reg_XXX): Likewise.
(index_arch_XXX): Move most to <sys/platform/x86.h>. Define
rest to FEATURE_INDEX_2.
(x86_get_cpuid_registers): New.
* sysdeps/x86/dl-get-cpu-features.c (x86_get_cpuid_registers):
Undef.
(x86_get_arch_feature): Likewise.
(x86_get_cpuid_registers): New function.
(x86_get_arch_feature): Likewise.
* sysdeps/x86/sys/platform/x86.h: New file.
* sysdeps/x86/tst-get-cpu-features.c: Include <stdio.h> and
<support/check.h>.
(cpu_kinds): New.
(do_test): Print vendor.
(TEST_FUNCTION): Removed.
Include <support/test-driver.c> instead of
"../../test-skeleton.c".
* sysdeps/x86/tst-x86-platform-1-static.c: New file.
* sysdeps/x86/tst-x86-platform-1.c: Likewise.
* sysdeps/x86/tst-x86-platform-2.c: Likewise.
* sysdeps/x86/tst-x86-platform-3.c: Likewise.
* sysdeps/x86/tst-x86-platform-mod-2.c: Likewise.
* sysdeps/x86/tst-x86-platform-mod-3.c: Likewise.
* sysdeps/x86_64/multiarch/sched_cpucount.c (__sched_cpucount):
Check POPCNT instead of POPCOUNT.
* sysdeps/x86_64/multiarch/test-multiarch.c (do_test): Likewise.
---
NEWS | 3 +
manual/platform.texi | 408 ++++++++++
sysdeps/mach/hurd/i386/ld.abilist | 2 +
sysdeps/unix/sysv/linux/i386/ld.abilist | 2 +
sysdeps/unix/sysv/linux/x86_64/64/ld.abilist | 2 +
sysdeps/unix/sysv/linux/x86_64/x32/ld.abilist | 2 +
sysdeps/x86/Makefile | 17 +-
sysdeps/x86/Versions | 3 +
sysdeps/x86/cpu-features.c | 97 ++-
sysdeps/x86/cpu-features.h | 239 ++----
sysdeps/x86/dl-get-cpu-features.c | 19 +
sysdeps/x86/sys/platform/x86.h | 753 ++++++++++++++++++
sysdeps/x86/tst-get-cpu-features.c | 29 +-
sysdeps/x86/tst-x86-platform-1-static.c | 1 +
sysdeps/x86/tst-x86-platform-1.c | 116 +++
sysdeps/x86/tst-x86-platform-2.c | 27 +
sysdeps/x86/tst-x86-platform-3.c | 27 +
sysdeps/x86/tst-x86-platform-mod-2.c | 2 +
sysdeps/x86/tst-x86-platform-mod-3.c | 2 +
sysdeps/x86_64/multiarch/sched_cpucount.c | 2 +-
sysdeps/x86_64/multiarch/test-multiarch.c | 4 +-
21 files changed, 1544 insertions(+), 213 deletions(-)
create mode 100644 sysdeps/x86/sys/platform/x86.h
create mode 100644 sysdeps/x86/tst-x86-platform-1-static.c
create mode 100644 sysdeps/x86/tst-x86-platform-1.c
create mode 100644 sysdeps/x86/tst-x86-platform-2.c
create mode 100644 sysdeps/x86/tst-x86-platform-3.c
create mode 100644 sysdeps/x86/tst-x86-platform-mod-2.c
create mode 100644 sysdeps/x86/tst-x86-platform-mod-3.c
@@ -9,6 +9,9 @@ Version 2.29
Major new features:
+* Add <sys/platform/x86.h> to provide an API to access x86 specific
+ platform features.
+
* A new convenience target has been added for distribution maintainers
to build and install all locales as directories with files. The new
target is run by issuing the following command in your build tree:
@@ -7,6 +7,7 @@
@menu
* PowerPC:: Facilities Specific to the PowerPC Architecture
* RISC-V:: Facilities Specific to the RISC-V Architecture
+* x86:: Facilities Specific to the x86 Architecture
@end menu
@node PowerPC
@@ -134,3 +135,410 @@ all threads in the current process. Setting the
ordering on only the current thread is necessary. All other flag bits are
reserved.
@end deftypefun
+
+@node x86
+@appendixsec x86-specific Facilities
+
+Facilities specific to x86 are declared in @file{<sys/platform/x86.h>}.
+
+@deftypefun {const struct cpuid_registers *} x86_get_cpuid_registers (unsigned int)
+
+Internal function used by @code{CPU_FEATURE_USABLE}.
+@end deftypefun
+
+@deftypefun {unsigned int} x86_get_arch_feature (unsigned int)
+
+Internal function used by @code{CPU_FEATURE_USABLE}.
+@end deftypefun
+
+@defmac CPU_FEATURE_USABLE (name)
+
+Evaluate to true if the architecture feature @code{name} is usable.
+The supported features are:
+
+@itemize @bullet
+
+@item
+@code{ACPI} -- Thermal Monitor and Software Controlled Clock Facilities.
+
+@item
+@code{ADX} -- ADX instruction extensions.
+
+@item
+@code{APIC} -- APIC On-Chip.
+
+@item
+@code{AES} -- The AES instruction extensions.
+
+@item
+@code{AVX} -- The AVX instruction extensions.
+
+@item
+@code{AVX2} -- The AVX2 instruction extensions.
+
+@item
+@code{AVX512_4FMAPS} -- The AVX512_4FMAPS instruction extensions.
+
+@item
+@code{AVX512_4VNNIW} -- The AVX512_4VNNIW instruction extensions.
+
+@item
+@code{AVX512_BITALG} -- The AVX512_BITALG instruction extensions.
+
+@item
+@code{AVX512_IFMA} -- The AVX512_IFMA instruction extensions.
+
+@item
+@code{AVX512_VBMI} -- The AVX512_VBMI instruction extensions.
+
+@item
+@code{AVX512_VBMI2} -- The AVX512_VBMI2 instruction extensions.
+
+@item
+@code{AVX512_VNNI} -- The AVX512_VNNI instruction extensions.
+
+@item
+@code{AVX512_VPOPCNTDQ} -- The AVX512_VPOPCNTDQ instruction extensions.
+
+@item
+@code{AVX512BW} -- The AVX512BW instruction extensions.
+
+@item
+@code{AVX512CD} -- The AVX512CD instruction extensions.
+
+@item
+@code{AVX512ER} -- The AVX512ER instruction extensions.
+
+@item
+@code{AVX512DQ} -- The AVX512DQ instruction extensions.
+
+@item
+@code{AVX512F} -- The AVX512F instruction extensions.
+
+@item
+@code{AVX512PF} -- The AVX512PF instruction extensions.
+
+@item
+@code{AVX512VL} -- The AVX512VL instruction extensions.
+
+@item
+@code{BMI1} -- BMI1 instructions.
+
+@item
+@code{BMI2} -- BMI2 instructions.
+
+@item
+@code{CLDEMOTE} -- CLDEMOTE instruction.
+
+@item
+@code{CLFLUSHOPT} -- CLFLUSHOPT instruction.
+
+@item
+@code{CLFSH} -- CLFLUSH instruction.
+
+@item
+@code{CLWB} -- CLWB instruction.
+
+@item
+@code{CMOV} -- Conditional Move instructions.
+
+@item
+@code{CMPXCHG16B} -- CMPXCHG16B instruction.
+
+@item
+@code{CNXT_ID} -- L1 Context ID.
+
+@item
+@code{CX8} -- CMPXCHG8B instruction.
+
+@item
+@code{DCA} -- Data prefetch from a memory mapped device.
+
+@item
+@code{DE} -- Debugging Extensions.
+
+@item
+@code{DS} -- Debug Store.
+
+@item
+@code{DS_CPL} -- CPL Qualified Debug Store.
+
+@item
+@code{DTES64} -- 64-bit DS Area.
+
+@item
+@code{EIST} -- Enhanced Intel SpeedStep technology.
+
+@item
+@code{ERMS} -- Enhanced REP MOVSB/STOSB.
+
+@item
+@code{F16C} -- 16-bit floating-point conversion instructions.
+
+@item
+@code{FMA} -- FMA extensions using YMM state.
+
+@item
+@code{FMA4} -- FMA4 instruction extensions.
+
+@item
+@code{FPU} -- X87 Floating Point Unit On-Chip.
+
+@item
+@code{FSGSBASE} -- RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instructions.
+
+@item
+@code{FSRM} -- Fast Short REP MOV.
+
+@item
+@code{FXSR} -- FXSAVE and FXRSTOR instructions.
+
+@item
+@code{GFNI} -- GFNI instruction extensions.
+
+@item
+@code{HLE} -- HLE instruction extensions.
+
+@item
+@code{HTT} -- Max APIC IDs reserved field is Valid.
+
+@item
+@code{IBT} -- Intel Indirect Branch Tracking instruction extensions.
+
+@item
+@code{INVPCID} -- INVPCID instruction.
+
+@item
+@code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode.
+
+@item
+@code{LZCNT} -- LZCNT instruction.
+
+@item
+@code{LM} -- Long mode.
+
+@item
+@code{LWP} -- Lightweight profiling.
+
+@item
+@code{MCA} -- Machine Check Architecture.
+
+@item
+@code{MCE} -- Machine Check Exception.
+
+@item
+@code{MMX} -- Intel MMX Technology.
+
+@item
+@code{MONITOR} -- MONITOR/MWAIT instructions.
+
+@item
+@code{MOVBE} -- MOVBE instruction.
+
+@item
+@code{MOVDIRI} -- MOVDIRI instruction.
+
+@item
+@code{MOVDIR64B} -- MOVDIR64B instruction.
+
+@item
+@code{MPX} -- Intel Memory Protection Extensions.
+
+@item
+@code{MSR} -- Model Specific Registers RDMSR and WRMSR instructions.
+
+@item
+@code{MTRR} -- Memory Type Range Registers.
+
+@item
+@code{NX} -- No-execute page protection.
+
+@item
+@code{OSPKE} -- OS has set CR4.PKE to enable protection keys.
+
+@item
+@code{OSXSAVE} -- The OS has set CR4.OSXSAVE[bit 18] to enable
+XSETBV/XGETBV instructions to access XCR0 and to support processor
+extended state management using XSAVE/XRSTOR.
+
+@item
+@code{PAE} -- Physical Address Extension.
+
+@item
+@code{PAGE1GB} -- 1-GByte page.
+
+@item
+@code{PAT} -- Page Attribute Table.
+
+@item
+@code{PBE} -- Pending Break Enable.
+
+@item
+@code{PCID} -- Process-context identifiers.
+
+@item
+@code{PCLMULQDQ} -- PCLMULQDQ instruction.
+
+@item
+@code{PCONFIG} -- PCONFIG instruction.
+
+@item
+@code{PDCM} -- Perfmon and Debug Capability.
+
+@item
+@code{PGE} -- Page Global Bit.
+
+@item
+@code{PKU} -- Protection keys for user-mode pages.
+
+@item
+@code{POPCNT} -- POPCNT instruction.
+
+@item
+@code{PQM} -- Platform Quality of Service Monitoring.
+
+@item
+@code{PQE} -- Platform Quality of Service Enforcement.
+
+@item
+@code{PREFETCHW} -- PREFETCHW instruction.
+
+@item
+@code{PREFETCHWT1} -- PREFETCHWT1 instruction.
+
+@item
+@code{PSE} -- Page Size Extension.
+
+@item
+@code{PSE_36} -- 36-Bit Page Size Extension.
+
+@item
+@code{PSN} -- Processor Serial Number.
+
+@item
+@code{RDPID} -- RDPID instruction.
+
+@item
+@code{RDRAND} -- RDRAND instruction.
+
+@item
+@code{RDSEED} -- RDSEED instruction.
+
+@item
+@code{RDTSCP} -- RDTSCP instruction.
+
+@item
+@code{RTM} -- RTM instruction extensions.
+
+@item
+@code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug.
+
+@item
+@code{SEP} -- SYSENTER and SYSEXIT instructions.
+
+@item
+@code{SGX} -- Intel Software Guard Extensions.
+
+@item
+@code{SGX_LC} -- SGX Launch Configuration.
+
+@item
+@code{SHA} -- SHA instruction extensions.
+
+@item
+@code{SHSTK} -- Intel Shadow Stack instruction extensions.
+
+@item
+@code{SMAP} -- Supervisor-Mode Access Prevention.
+
+@item
+@code{SMEP} -- Supervisor-Mode Execution Prevention.
+
+@item
+@code{SMX} -- Safer Mode Extensions.
+
+@item
+@code{SS} -- Self Snoop.
+
+@item
+@code{SSE} -- Streaming SIMD Extensions.
+
+@item
+@code{SSE2} -- Streaming SIMD Extensions 2.
+
+@item
+@code{SSE3} -- Streaming SIMD Extensions 3.
+
+@item
+@code{SSE4_1} -- Streaming SIMD Extensions 4.1.
+
+@item
+@code{SSE4_2} -- Streaming SIMD Extensions 4.2.
+
+@item
+@code{SSE4A} -- SSE4A instruction extensions.
+
+@item
+@code{SSSE3} -- Supplemental Streaming SIMD Extensions 3.
+
+@item
+@code{SVM} -- Secure Virtual Machine.
+
+@item
+@code{SYSCALL_SYSRET} -- SYSCALL/SYSRET instructions.
+
+@item
+@code{TBM} -- Trailing bit manipulation instructions.
+
+@item
+@code{TM} -- Thermal Monitor.
+
+@item
+@code{TM2} -- Thermal Monitor 2.
+
+@item
+@code{TRACE} -- Intel Processor Trace.
+
+@item
+@code{TSC} -- Time Stamp Counter. RDTSC instruction.
+
+@item
+@code{TSC_ADJUST} -- IA32_TSC_ADJUST MSR.
+
+@item
+@code{TSC_DEADLINE} -- Local APIC timer supports one-shot operation
+using a TSC deadline value.
+
+@item
+@code{UMIP} -- User-mode instruction prevention.
+
+@item
+@code{VAES} -- VAES instruction extensions.
+
+@item
+@code{VME} -- Virtual 8086 Mode Enhancements.
+
+@item
+@code{VMX} -- Virtual Machine Extensions.
+
+@item
+@code{VPCLMULQDQ} -- VPCLMULQDQ instruction.
+
+@item
+@code{WAITPKG} -- WAITPKG instruction extensions.
+
+@item
+@code{X2APIC} -- x2APIC.
+
+@item
+@code{XOP} -- XOP instruction extensions.
+
+@item
+@code{XSAVE} -- The XSAVE/XRSTOR processor extended states feature, the
+XSETBV/XGETBV instructions, and XCR0.
+
+@item
+@code{XTPRUPDCTRL} -- xTPR Update Control.
+
+@end itemize
+@end defmac
@@ -20,6 +20,8 @@ GLIBC_2.2.6 calloc F
GLIBC_2.2.6 free F
GLIBC_2.2.6 malloc F
GLIBC_2.2.6 realloc F
+GLIBC_2.29 x86_get_arch_feature F
+GLIBC_2.29 x86_get_cpuid_registers F
GLIBC_2.3 ___tls_get_addr F
GLIBC_2.3 __tls_get_addr F
GLIBC_2.4 __stack_chk_guard D 0x4
@@ -5,5 +5,7 @@ GLIBC_2.0 malloc F
GLIBC_2.0 realloc F
GLIBC_2.1 __libc_stack_end D 0x4
GLIBC_2.1 _dl_mcount F
+GLIBC_2.29 x86_get_arch_feature F
+GLIBC_2.29 x86_get_cpuid_registers F
GLIBC_2.3 ___tls_get_addr F
GLIBC_2.3 __tls_get_addr F
@@ -5,4 +5,6 @@ GLIBC_2.2.5 calloc F
GLIBC_2.2.5 free F
GLIBC_2.2.5 malloc F
GLIBC_2.2.5 realloc F
+GLIBC_2.29 x86_get_arch_feature F
+GLIBC_2.29 x86_get_cpuid_registers F
GLIBC_2.3 __tls_get_addr F
@@ -6,3 +6,5 @@ GLIBC_2.16 calloc F
GLIBC_2.16 free F
GLIBC_2.16 malloc F
GLIBC_2.16 realloc F
+GLIBC_2.29 x86_get_arch_feature F
+GLIBC_2.29 x86_get_cpuid_registers F
@@ -5,8 +5,21 @@ endif
ifeq ($(subdir),elf)
sysdep-dl-routines += dl-get-cpu-features
-tests += tst-get-cpu-features tst-get-cpu-features-static
-tests-static += tst-get-cpu-features-static
+tests += tst-get-cpu-features tst-get-cpu-features-static \
+ tst-x86-platform-1 tst-x86-platform-1-static \
+ tst-x86-platform-2 tst-x86-platform-3
+modules-names += tst-x86-platform-mod-2 tst-x86-platform-mod-3
+tests-static += tst-get-cpu-features-static tst-x86-platform-1-static
+
+$(objpfx)tst-x86-platform-mod-2.so: $(libsupport)
+$(objpfx)tst-x86-platform-2: $(objpfx)tst-x86-platform-mod-2.so
+LDFLAGS-tst-x86-platform-mod-3.so = -Wl,-z,now
+$(objpfx)tst-x86-platform-mod-3.so: $(libsupport)
+$(objpfx)tst-x86-platform-3: $(objpfx)tst-x86-platform-mod-3.so
+endif
+
+ifeq ($(subdir),misc)
+sysdep_headers += sys/platform/x86.h
endif
ifeq ($(subdir),setjmp)
@@ -1,4 +1,7 @@
ld {
+ GLIBC_2.29 {
+ x86_get_cpuid_registers; x86_get_arch_feature;
+ }
GLIBC_PRIVATE {
__get_cpu_features;
}
@@ -117,6 +117,18 @@ get_common_indices (struct cpu_features *cpu_features,
if (CPU_FEATURES_CPU_P (cpu_features, FMA))
cpu_features->feature[index_arch_FMA_Usable]
|= bit_arch_FMA_Usable;
+ /* Determine if VAES is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, VAES))
+ cpu_features->feature[index_arch_VAES_Usable]
+ |= bit_arch_VAES_Usable;
+ /* Determine if VPCLMULQDQ is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, VPCLMULQDQ))
+ cpu_features->feature[index_arch_VPCLMULQDQ_Usable]
+ |= bit_arch_VPCLMULQDQ_Usable;
+ /* Determine if XOP is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, XOP))
+ cpu_features->feature[index_arch_XOP_Usable]
+ |= bit_arch_XOP_Usable;
}
/* Check if OPMASK state, upper 256-bit of ZMM0-ZMM15 and
@@ -130,10 +142,62 @@ get_common_indices (struct cpu_features *cpu_features,
{
cpu_features->feature[index_arch_AVX512F_Usable]
|= bit_arch_AVX512F_Usable;
+ /* Determine if AVX512CD is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512CD))
+ cpu_features->feature[index_arch_AVX512CD_Usable]
+ |= bit_arch_AVX512CD_Usable;
+ /* Determine if AVX512ER is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512ER))
+ cpu_features->feature[index_arch_AVX512ER_Usable]
+ |= bit_arch_AVX512ER_Usable;
+ /* Determine if AVX512PF is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512PF))
+ cpu_features->feature[index_arch_AVX512PF_Usable]
+ |= bit_arch_AVX512PF_Usable;
+ /* Determine if AVX512VL is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512VL))
+ cpu_features->feature[index_arch_AVX512VL_Usable]
+ |= bit_arch_AVX512VL_Usable;
/* Determine if AVX512DQ is usable. */
if (CPU_FEATURES_CPU_P (cpu_features, AVX512DQ))
cpu_features->feature[index_arch_AVX512DQ_Usable]
|= bit_arch_AVX512DQ_Usable;
+ /* Determine if AVX512BW is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512BW))
+ cpu_features->feature[index_arch_AVX512BW_Usable]
+ |= bit_arch_AVX512BW_Usable;
+ /* Determine if AVX512_4FMAPS is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512_4FMAPS))
+ cpu_features->feature[index_arch_AVX512_4FMAPS_Usable]
+ |= bit_arch_AVX512_4FMAPS_Usable;
+ /* Determine if AVX512_4VNNIW is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512_4VNNIW))
+ cpu_features->feature[index_arch_AVX512_4VNNIW_Usable]
+ |= bit_arch_AVX512_4VNNIW_Usable;
+ /* Determine if AVX512_BITALG is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512_BITALG))
+ cpu_features->feature[index_arch_AVX512_BITALG_Usable]
+ |= bit_arch_AVX512_BITALG_Usable;
+ /* Determine if AVX512_IFMA is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512_IFMA))
+ cpu_features->feature[index_arch_AVX512_IFMA_Usable]
+ |= bit_arch_AVX512_IFMA_Usable;
+ /* Determine if AVX512_VBMI is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512_VBMI))
+ cpu_features->feature[index_arch_AVX512_VBMI_Usable]
+ |= bit_arch_AVX512_VBMI_Usable;
+ /* Determine if AVX512_VBMI2 is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512_VBMI2))
+ cpu_features->feature[index_arch_AVX512_VBMI2_Usable]
+ |= bit_arch_AVX512_VBMI2_Usable;
+ /* Determine if is AVX512_VNNI usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512_VNNI))
+ cpu_features->feature[index_arch_AVX512_VNNI_Usable]
+ |= bit_arch_AVX512_VNNI_Usable;
+ /* Determine if AVX512_VPOPCNTDQ is usable. */
+ if (CPU_FEATURES_CPU_P (cpu_features, AVX512_VPOPCNTDQ))
+ cpu_features->feature[index_arch_AVX512_VPOPCNTDQ_Usable]
+ |= bit_arch_AVX512_VPOPCNTDQ_Usable;
}
}
}
@@ -210,6 +274,18 @@ get_common_indices (struct cpu_features *cpu_features,
}
}
+_Static_assert (((index_arch_Fast_Unaligned_Load
+ == index_arch_Fast_Unaligned_Copy)
+ && (index_arch_Fast_Unaligned_Load
+ == index_arch_Prefer_PMINUB_for_stringop)
+ && (index_arch_Fast_Unaligned_Load
+ == index_arch_Slow_SSE4_2)
+ && (index_arch_Fast_Unaligned_Load
+ == index_arch_Fast_Rep_String)
+ && (index_arch_Fast_Unaligned_Load
+ == index_arch_Fast_Copy_Backward)),
+ "Incorrect index_arch_Fast_Unaligned_Load");
+
static inline void
init_cpu_features (struct cpu_features *cpu_features)
{
@@ -270,15 +346,6 @@ init_cpu_features (struct cpu_features *cpu_features)
case 0x5d:
/* Unaligned load versions are faster than SSSE3
on Silvermont. */
-#if index_arch_Fast_Unaligned_Load != index_arch_Prefer_PMINUB_for_stringop
-# error index_arch_Fast_Unaligned_Load != index_arch_Prefer_PMINUB_for_stringop
-#endif
-#if index_arch_Fast_Unaligned_Load != index_arch_Slow_SSE4_2
-# error index_arch_Fast_Unaligned_Load != index_arch_Slow_SSE4_2
-#endif
-#if index_arch_Fast_Unaligned_Load != index_arch_Fast_Unaligned_Copy
-# error index_arch_Fast_Unaligned_Load != index_arch_Fast_Unaligned_Copy
-#endif
cpu_features->feature[index_arch_Fast_Unaligned_Load]
|= (bit_arch_Fast_Unaligned_Load
| bit_arch_Fast_Unaligned_Copy
@@ -301,15 +368,6 @@ init_cpu_features (struct cpu_features *cpu_features)
case 0x2f:
/* Rep string instructions, unaligned load, unaligned copy,
and pminub are fast on Intel Core i3, i5 and i7. */
-#if index_arch_Fast_Rep_String != index_arch_Fast_Unaligned_Load
-# error index_arch_Fast_Rep_String != index_arch_Fast_Unaligned_Load
-#endif
-#if index_arch_Fast_Rep_String != index_arch_Prefer_PMINUB_for_stringop
-# error index_arch_Fast_Rep_String != index_arch_Prefer_PMINUB_for_stringop
-#endif
-#if index_arch_Fast_Rep_String != index_arch_Fast_Unaligned_Copy
-# error index_arch_Fast_Rep_String != index_arch_Fast_Unaligned_Copy
-#endif
cpu_features->feature[index_arch_Fast_Rep_String]
|= (bit_arch_Fast_Rep_String
| bit_arch_Fast_Unaligned_Load
@@ -375,9 +433,6 @@ init_cpu_features (struct cpu_features *cpu_features)
if (family == 0x15)
{
-#if index_arch_Fast_Unaligned_Load != index_arch_Fast_Copy_Backward
-# error index_arch_Fast_Unaligned_Load != index_arch_Fast_Copy_Backward
-#endif
/* "Excavator" */
if (model >= 0x60 && model <= 0x7f)
{
@@ -18,106 +18,63 @@
#ifndef cpu_features_h
#define cpu_features_h
-#define bit_arch_Fast_Rep_String (1 << 0)
-#define bit_arch_Fast_Copy_Backward (1 << 1)
-#define bit_arch_Slow_BSF (1 << 2)
-#define bit_arch_Fast_Unaligned_Load (1 << 4)
-#define bit_arch_Prefer_PMINUB_for_stringop (1 << 5)
-#define bit_arch_AVX_Usable (1 << 6)
-#define bit_arch_FMA_Usable (1 << 7)
-#define bit_arch_FMA4_Usable (1 << 8)
-#define bit_arch_Slow_SSE4_2 (1 << 9)
-#define bit_arch_AVX2_Usable (1 << 10)
-#define bit_arch_AVX_Fast_Unaligned_Load (1 << 11)
-#define bit_arch_AVX512F_Usable (1 << 12)
-#define bit_arch_AVX512DQ_Usable (1 << 13)
-#define bit_arch_I586 (1 << 14)
-#define bit_arch_I686 (1 << 15)
-#define bit_arch_Prefer_MAP_32BIT_EXEC (1 << 16)
-#define bit_arch_Prefer_No_VZEROUPPER (1 << 17)
-#define bit_arch_Fast_Unaligned_Copy (1 << 18)
-#define bit_arch_Prefer_ERMS (1 << 19)
-#define bit_arch_Prefer_No_AVX512 (1 << 20)
-#define bit_arch_MathVec_Prefer_No_AVX512 (1 << 21)
-#define bit_arch_XSAVEC_Usable (1 << 22)
-#define bit_arch_Prefer_FSRM (1 << 23)
-
-/* CPUID Feature flags. */
-
-/* COMMON_CPUID_INDEX_1. */
-#define bit_cpu_CX8 (1 << 8)
-#define bit_cpu_CMOV (1 << 15)
-#define bit_cpu_SSE (1 << 25)
-#define bit_cpu_SSE2 (1 << 26)
-#define bit_cpu_SSSE3 (1 << 9)
-#define bit_cpu_SSE4_1 (1 << 19)
-#define bit_cpu_SSE4_2 (1 << 20)
-#define bit_cpu_OSXSAVE (1 << 27)
-#define bit_cpu_AVX (1 << 28)
-#define bit_cpu_POPCOUNT (1 << 23)
-#define bit_cpu_FMA (1 << 12)
-#define bit_cpu_FMA4 (1 << 16)
-#define bit_cpu_HTT (1 << 28)
-#define bit_cpu_LZCNT (1 << 5)
-#define bit_cpu_MOVBE (1 << 22)
-#define bit_cpu_POPCNT (1 << 23)
-
-/* COMMON_CPUID_INDEX_7. */
-#define bit_cpu_BMI1 (1 << 3)
-#define bit_cpu_BMI2 (1 << 8)
-#define bit_cpu_ERMS (1 << 9)
-#define bit_cpu_RTM (1 << 11)
-#define bit_cpu_AVX2 (1 << 5)
-#define bit_cpu_AVX512F (1 << 16)
-#define bit_cpu_AVX512DQ (1 << 17)
-#define bit_cpu_AVX512PF (1 << 26)
-#define bit_cpu_AVX512ER (1 << 27)
-#define bit_cpu_AVX512CD (1 << 28)
-#define bit_cpu_AVX512BW (1 << 30)
-#define bit_cpu_AVX512VL (1u << 31)
-#define bit_cpu_IBT (1u << 20)
-#define bit_cpu_SHSTK (1u << 7)
-#define bit_cpu_FSRM (1 << 4)
+#include <sys/platform/x86.h>
+
+/* FEATURE_INDEX_2. */
+#define bit_arch_I586 (1u << 0)
+#define bit_arch_I686 (1u << 1)
+#define bit_arch_Fast_Rep_String (1u << 2)
+#define bit_arch_Fast_Copy_Backward (1u << 3)
+#define bit_arch_Fast_Unaligned_Load (1u << 4)
+#define bit_arch_Fast_Unaligned_Copy (1u << 5)
+#define bit_arch_Slow_BSF (1u << 6)
+#define bit_arch_Slow_SSE4_2 (1u << 7)
+#define bit_arch_AVX_Fast_Unaligned_Load (1u << 8)
+#define bit_arch_Prefer_MAP_32BIT_EXEC (1u << 9)
+#define bit_arch_Prefer_PMINUB_for_stringop (1u << 10)
+#define bit_arch_Prefer_No_VZEROUPPER (1u << 11)
+#define bit_arch_Prefer_ERMS (1u << 12)
+#define bit_arch_Prefer_FSRM (1u << 13)
+#define bit_arch_Prefer_No_AVX512 (1u << 14)
+#define bit_arch_MathVec_Prefer_No_AVX512 (1u << 15)
+
+#define index_arch_Fast_Rep_String FEATURE_INDEX_2
+#define index_arch_Fast_Copy_Backward FEATURE_INDEX_2
+#define index_arch_Slow_BSF FEATURE_INDEX_2
+#define index_arch_Fast_Unaligned_Load FEATURE_INDEX_2
+#define index_arch_Prefer_PMINUB_for_stringop FEATURE_INDEX_2
+#define index_arch_Fast_Unaligned_Copy FEATURE_INDEX_2
+#define index_arch_I586 FEATURE_INDEX_2
+#define index_arch_I686 FEATURE_INDEX_2
+#define index_arch_Slow_SSE4_2 FEATURE_INDEX_2
+#define index_arch_AVX_Fast_Unaligned_Load FEATURE_INDEX_2
+#define index_arch_Prefer_MAP_32BIT_EXEC FEATURE_INDEX_2
+#define index_arch_Prefer_No_VZEROUPPER FEATURE_INDEX_2
+#define index_arch_Prefer_ERMS FEATURE_INDEX_2
+#define index_arch_Prefer_No_AVX512 FEATURE_INDEX_2
+#define index_arch_MathVec_Prefer_No_AVX512 FEATURE_INDEX_2
+#define index_arch_Prefer_FSRM FEATURE_INDEX_2
/* XCR0 Feature flags. */
-#define bit_XMM_state (1 << 1)
-#define bit_YMM_state (1 << 2)
-#define bit_Opmask_state (1 << 5)
-#define bit_ZMM0_15_state (1 << 6)
-#define bit_ZMM16_31_state (1 << 7)
-
-/* The integer bit array index for the first set of internal feature bits. */
-#define FEATURE_INDEX_1 0
-
-/* The current maximum size of the feature integer bit array. */
-#define FEATURE_INDEX_MAX 1
+#define bit_XMM_state (1u << 1)
+#define bit_YMM_state (1u << 2)
+#define bit_Opmask_state (1u << 5)
+#define bit_ZMM0_15_state (1u << 6)
+#define bit_ZMM16_31_state (1u << 7)
-enum
+enum cpu_features_kind
{
- COMMON_CPUID_INDEX_1 = 0,
- COMMON_CPUID_INDEX_7,
- COMMON_CPUID_INDEX_80000001,
- /* Keep the following line at the end. */
- COMMON_CPUID_INDEX_MAX
+ arch_kind_unknown = 0,
+ arch_kind_intel,
+ arch_kind_amd,
+ arch_kind_other
};
struct cpu_features
{
- enum cpu_features_kind
- {
- arch_kind_unknown = 0,
- arch_kind_intel,
- arch_kind_amd,
- arch_kind_other
- } kind;
+ enum cpu_features_kind kind;
int max_cpuid;
- struct cpuid_registers
- {
- unsigned int eax;
- unsigned int ebx;
- unsigned int ecx;
- unsigned int edx;
- } cpuid[COMMON_CPUID_INDEX_MAX];
+ struct cpuid_registers cpuid[COMMON_CPUID_INDEX_MAX];
unsigned int family;
unsigned int model;
/* The state size for XSAVEC or XSAVE. The type must be unsigned long
@@ -152,6 +109,8 @@ extern const struct cpu_features *__get_cpu_features (void)
/* Unused for x86. */
# define INIT_ARCH()
# define __get_cpu_features() (&GLRO(dl_x86_cpu_features))
+# define x86_get_cpuid_registers(i) \
+ (&(GLRO(dl_x86_cpu_features).cpuid[i]))
# endif
@@ -161,99 +120,13 @@ extern const struct cpu_features *__get_cpu_features (void)
# define CPU_FEATURES_ARCH_P(ptr, name) \
((ptr->feature[index_arch_##name] & (bit_arch_##name)) != 0)
-/* HAS_* evaluates to true if we may use the feature at runtime. */
-# define HAS_CPU_FEATURE(name) \
- CPU_FEATURES_CPU_P (__get_cpu_features (), name)
+/* HAS_CPU_FEATURE evaluates to true if CPU supports the feature. */
+#define HAS_CPU_FEATURE(name) \
+ CPU_FEATURES_CPU_P (__get_cpu_features (), name)
+/* HAS_ARCH_FEATURE evaluates to true if we may use the feature at
+ runtime. */
# define HAS_ARCH_FEATURE(name) \
- CPU_FEATURES_ARCH_P (__get_cpu_features (), name)
-
-# define index_cpu_CX8 COMMON_CPUID_INDEX_1
-# define index_cpu_CMOV COMMON_CPUID_INDEX_1
-# define index_cpu_SSE COMMON_CPUID_INDEX_1
-# define index_cpu_SSE2 COMMON_CPUID_INDEX_1
-# define index_cpu_SSSE3 COMMON_CPUID_INDEX_1
-# define index_cpu_SSE4_1 COMMON_CPUID_INDEX_1
-# define index_cpu_SSE4_2 COMMON_CPUID_INDEX_1
-# define index_cpu_AVX COMMON_CPUID_INDEX_1
-# define index_cpu_AVX2 COMMON_CPUID_INDEX_7
-# define index_cpu_AVX512F COMMON_CPUID_INDEX_7
-# define index_cpu_AVX512DQ COMMON_CPUID_INDEX_7
-# define index_cpu_AVX512PF COMMON_CPUID_INDEX_7
-# define index_cpu_AVX512ER COMMON_CPUID_INDEX_7
-# define index_cpu_AVX512CD COMMON_CPUID_INDEX_7
-# define index_cpu_AVX512BW COMMON_CPUID_INDEX_7
-# define index_cpu_AVX512VL COMMON_CPUID_INDEX_7
-# define index_cpu_ERMS COMMON_CPUID_INDEX_7
-# define index_cpu_RTM COMMON_CPUID_INDEX_7
-# define index_cpu_FMA COMMON_CPUID_INDEX_1
-# define index_cpu_FMA4 COMMON_CPUID_INDEX_80000001
-# define index_cpu_POPCOUNT COMMON_CPUID_INDEX_1
-# define index_cpu_OSXSAVE COMMON_CPUID_INDEX_1
-# define index_cpu_HTT COMMON_CPUID_INDEX_1
-# define index_cpu_BMI1 COMMON_CPUID_INDEX_7
-# define index_cpu_BMI2 COMMON_CPUID_INDEX_7
-# define index_cpu_LZCNT COMMON_CPUID_INDEX_80000001
-# define index_cpu_MOVBE COMMON_CPUID_INDEX_1
-# define index_cpu_POPCNT COMMON_CPUID_INDEX_1
-# define index_cpu_IBT COMMON_CPUID_INDEX_7
-# define index_cpu_SHSTK COMMON_CPUID_INDEX_7
-# define index_cpu_FSRM COMMON_CPUID_INDEX_7
-
-# define reg_CX8 edx
-# define reg_CMOV edx
-# define reg_SSE edx
-# define reg_SSE2 edx
-# define reg_SSSE3 ecx
-# define reg_SSE4_1 ecx
-# define reg_SSE4_2 ecx
-# define reg_AVX ecx
-# define reg_AVX2 ebx
-# define reg_AVX512F ebx
-# define reg_AVX512DQ ebx
-# define reg_AVX512PF ebx
-# define reg_AVX512ER ebx
-# define reg_AVX512CD ebx
-# define reg_AVX512BW ebx
-# define reg_AVX512VL ebx
-# define reg_ERMS ebx
-# define reg_RTM ebx
-# define reg_FMA ecx
-# define reg_FMA4 ecx
-# define reg_POPCOUNT ecx
-# define reg_OSXSAVE ecx
-# define reg_HTT edx
-# define reg_BMI1 ebx
-# define reg_BMI2 ebx
-# define reg_LZCNT ecx
-# define reg_MOVBE ecx
-# define reg_POPCNT ecx
-# define reg_IBT edx
-# define reg_SHSTK ecx
-# define reg_FSRM edx
-
-# define index_arch_Fast_Rep_String FEATURE_INDEX_1
-# define index_arch_Fast_Copy_Backward FEATURE_INDEX_1
-# define index_arch_Slow_BSF FEATURE_INDEX_1
-# define index_arch_Fast_Unaligned_Load FEATURE_INDEX_1
-# define index_arch_Prefer_PMINUB_for_stringop FEATURE_INDEX_1
-# define index_arch_AVX_Usable FEATURE_INDEX_1
-# define index_arch_FMA_Usable FEATURE_INDEX_1
-# define index_arch_FMA4_Usable FEATURE_INDEX_1
-# define index_arch_Slow_SSE4_2 FEATURE_INDEX_1
-# define index_arch_AVX2_Usable FEATURE_INDEX_1
-# define index_arch_AVX_Fast_Unaligned_Load FEATURE_INDEX_1
-# define index_arch_AVX512F_Usable FEATURE_INDEX_1
-# define index_arch_AVX512DQ_Usable FEATURE_INDEX_1
-# define index_arch_I586 FEATURE_INDEX_1
-# define index_arch_I686 FEATURE_INDEX_1
-# define index_arch_Prefer_MAP_32BIT_EXEC FEATURE_INDEX_1
-# define index_arch_Prefer_No_VZEROUPPER FEATURE_INDEX_1
-# define index_arch_Fast_Unaligned_Copy FEATURE_INDEX_1
-# define index_arch_Prefer_ERMS FEATURE_INDEX_1
-# define index_arch_Prefer_No_AVX512 FEATURE_INDEX_1
-# define index_arch_MathVec_Prefer_No_AVX512 FEATURE_INDEX_1
-# define index_arch_XSAVEC_Usable FEATURE_INDEX_1
-# define index_arch_Prefer_FSRM FEATURE_INDEX_1
+ CPU_FEATURES_ARCH_P (__get_cpu_features (), name)
#ifdef __x86_64__
# define HAS_CPUID 1
@@ -19,9 +19,28 @@
#include <ldsodefs.h>
#undef __get_cpu_features
+#undef x86_get_cpuid_registers
+#undef x86_get_arch_feature
const struct cpu_features *
__get_cpu_features (void)
{
return &GLRO(dl_x86_cpu_features);
}
+
+const struct cpuid_registers *
+x86_get_cpuid_registers (unsigned int i)
+{
+ const static struct cpuid_registers zero_cpuid_registers = { 0 };
+ if (i >= COMMON_CPUID_INDEX_MAX)
+ return &zero_cpuid_registers;
+ return &GLRO(dl_x86_cpu_features).cpuid[i];
+}
+
+unsigned int
+x86_get_arch_feature (unsigned int i)
+{
+ if (i >= COMMON_CPUID_INDEX_MAX)
+ return 0;
+ return GLRO(dl_x86_cpu_features).feature[i];
+}
new file mode 100644
@@ -0,0 +1,753 @@
+/* Facilities specific to the x86 architecture.
+ Copyright (C) 2018 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef _SYS_PLATFORM_X86_H
+#define _SYS_PLATFORM_X86_H
+
+#include <sys/cdefs.h>
+
+__BEGIN_DECLS
+
+enum
+ {
+ /* The integer bit array index for the first set of internal feature
+ bits. */
+ FEATURE_INDEX_1 = 0,
+ FEATURE_INDEX_2,
+ /* The current maximum size of the feature integer bit array. */
+ FEATURE_INDEX_MAX
+ };
+
+enum
+ {
+ COMMON_CPUID_INDEX_1 = 0,
+ COMMON_CPUID_INDEX_7,
+ COMMON_CPUID_INDEX_80000001,
+ /* Keep the following line at the end. */
+ COMMON_CPUID_INDEX_MAX
+ };
+
+struct cpuid_registers
+ {
+ unsigned int eax;
+ unsigned int ebx;
+ unsigned int ecx;
+ unsigned int edx;
+ };
+
+extern const struct cpuid_registers *x86_get_cpuid_registers
+ (unsigned int) __attribute__ ((const));
+
+extern unsigned int x86_get_arch_feature (unsigned int)
+ __attribute__ ((const));
+
+/* CPU_FEATURE_USABLE evaluates to true if the feature is usable. */
+#define CPU_FEATURE_USABLE(name) \
+ ((need_arch_feature_##name \
+ && (x86_get_arch_feature (index_arch_##name##_Usable) \
+ & (bit_arch_##name##_Usable)) != 0) \
+ || (!need_arch_feature_##name \
+ && (x86_get_cpuid_registers (index_cpu_##name)->reg_##name \
+ & (bit_cpu_##name)) != 0))
+
+/* Architecture features. */
+
+/* FEATURE_INDEX_1. */
+#define bit_arch_AVX_Usable (1u << 0)
+#define bit_arch_AVX2_Usable (1u << 1)
+#define bit_arch_AVX512F_Usable (1u << 2)
+#define bit_arch_AVX512CD_Usable (1u << 3)
+#define bit_arch_AVX512ER_Usable (1u << 4)
+#define bit_arch_AVX512PF_Usable (1u << 5)
+#define bit_arch_AVX512VL_Usable (1u << 6)
+#define bit_arch_AVX512DQ_Usable (1u << 7)
+#define bit_arch_AVX512BW_Usable (1u << 8)
+#define bit_arch_AVX512_4FMAPS_Usable (1u << 9)
+#define bit_arch_AVX512_4VNNIW_Usable (1u << 10)
+#define bit_arch_AVX512_BITALG_Usable (1u << 11)
+#define bit_arch_AVX512_IFMA_Usable (1u << 12)
+#define bit_arch_AVX512_VBMI_Usable (1u << 13)
+#define bit_arch_AVX512_VBMI2_Usable (1u << 14)
+#define bit_arch_AVX512_VNNI_Usable (1u << 15)
+#define bit_arch_AVX512_VPOPCNTDQ_Usable (1u << 16)
+#define bit_arch_FMA_Usable (1u << 17)
+#define bit_arch_FMA4_Usable (1u << 18)
+#define bit_arch_VAES_Usable (1u << 19)
+#define bit_arch_VPCLMULQDQ_Usable (1u << 20)
+#define bit_arch_XOP_Usable (1u << 21)
+#define bit_arch_XSAVEC_Usable (1u << 22)
+
+#define index_arch_AVX_Usable FEATURE_INDEX_1
+#define index_arch_AVX2_Usable FEATURE_INDEX_1
+#define index_arch_AVX512F_Usable FEATURE_INDEX_1
+#define index_arch_AVX512CD_Usable FEATURE_INDEX_1
+#define index_arch_AVX512ER_Usable FEATURE_INDEX_1
+#define index_arch_AVX512PF_Usable FEATURE_INDEX_1
+#define index_arch_AVX512VL_Usable FEATURE_INDEX_1
+#define index_arch_AVX512BW_Usable FEATURE_INDEX_1
+#define index_arch_AVX512DQ_Usable FEATURE_INDEX_1
+#define index_arch_AVX512_4FMAPS_Usable FEATURE_INDEX_1
+#define index_arch_AVX512_4VNNIW_Usable FEATURE_INDEX_1
+#define index_arch_AVX512_BITALG_Usable FEATURE_INDEX_1
+#define index_arch_AVX512_IFMA_Usable FEATURE_INDEX_1
+#define index_arch_AVX512_VBMI_Usable FEATURE_INDEX_1
+#define index_arch_AVX512_VBMI2_Usable FEATURE_INDEX_1
+#define index_arch_AVX512_VNNI_Usable FEATURE_INDEX_1
+#define index_arch_AVX512_VPOPCNTDQ_Usable FEATURE_INDEX_1
+#define index_arch_FMA_Usable FEATURE_INDEX_1
+#define index_arch_FMA4_Usable FEATURE_INDEX_1
+#define index_arch_VAES_Usable FEATURE_INDEX_1
+#define index_arch_VPCLMULQDQ_Usable FEATURE_INDEX_1
+#define index_arch_XOP_Usable FEATURE_INDEX_1
+#define index_arch_XSAVEC_Usable FEATURE_INDEX_1
+
+/* Unused. Compiler will optimize them out. */
+#define bit_arch_SSE3_Usable (1u << 0)
+#define bit_arch_PCLMULQDQ_Usable (1u << 0)
+#define bit_arch_SSSE3_Usable (1u << 0)
+#define bit_arch_CMPXCHG16B_Usable (1u << 0)
+#define bit_arch_SSE4_1_Usable (1u << 0)
+#define bit_arch_SSE4_2_Usable (1u << 0)
+#define bit_arch_MOVBE_Usable (1u << 0)
+#define bit_arch_POPCNT_Usable (1u << 0)
+#define bit_arch_AES_Usable (1u << 0)
+#define bit_arch_XSAVE_Usable (1u << 0)
+#define bit_arch_OSXSAVE_Usable (1u << 0)
+#define bit_arch_F16C_Usable (1u << 0)
+#define bit_arch_RDRAND_Usable (1u << 0)
+#define bit_arch_FPU_Usable (1u << 0)
+#define bit_arch_TSC_Usable (1u << 0)
+#define bit_arch_MSR_Usable (1u << 0)
+#define bit_arch_CX8_Usable (1u << 0)
+#define bit_arch_SEP_Usable (1u << 0)
+#define bit_arch_CMOV_Usable (1u << 0)
+#define bit_arch_CLFSH_Usable (1u << 0)
+#define bit_arch_MMX_Usable (1u << 0)
+#define bit_arch_FXSR_Usable (1u << 0)
+#define bit_arch_SSE_Usable (1u << 0)
+#define bit_arch_SSE2_Usable (1u << 0)
+#define bit_arch_FSGSBASE_Usable (1u << 0)
+#define bit_arch_BMI1_Usable (1u << 0)
+#define bit_arch_HLE_Usable (1u << 0)
+#define bit_arch_BMI2_Usable (1u << 0)
+#define bit_arch_ERMS_Usable (1u << 0)
+#define bit_arch_RTM_Usable (1u << 0)
+#define bit_arch_RDSEED_Usable (1u << 0)
+#define bit_arch_ADX_Usable (1u << 0)
+#define bit_arch_CLFLUSHOPT_Usable (1u << 0)
+#define bit_arch_CLWB_Usable (1u << 0)
+#define bit_arch_SHA_Usable (1u << 0)
+#define bit_arch_PREFETCHWT1_Usable (1u << 0)
+#define bit_arch_GFNI_Usable (1u << 0)
+#define bit_arch_RDPID_Usable (1u << 0)
+#define bit_arch_CLDEMOTE_Usable (1u << 0)
+#define bit_arch_MOVDIRI_Usable (1u << 0)
+#define bit_arch_MOVDIR64B_Usable (1u << 0)
+#define bit_arch_FSRM_Usable (1u << 0)
+#define bit_arch_LAHF64_SAHF64_Usable (1u << 0)
+#define bit_arch_SVM_Usable (1u << 0)
+#define bit_arch_LZCNT_Usable (1u << 0)
+#define bit_arch_SSE4A_Usable (1u << 0)
+#define bit_arch_PREFETCHW_Usable (1u << 0)
+#define bit_arch_TBM_Usable (1u << 0)
+#define bit_arch_SYSCALL_SYSRET_Usable (1u << 0)
+#define bit_arch_RDTSCP_Usable (1u << 0)
+
+/* Unused. Compiler will optimize them out. */
+#define index_arch_SSE3_Usable FEATURE_INDEX_1
+#define index_arch_PCLMULQDQ_Usable FEATURE_INDEX_1
+#define index_arch_SSSE3_Usable FEATURE_INDEX_1
+#define index_arch_CMPXCHG16B_Usable FEATURE_INDEX_1
+#define index_arch_SSE4_1_Usable FEATURE_INDEX_1
+#define index_arch_SSE4_2_Usable FEATURE_INDEX_1
+#define index_arch_MOVBE_Usable FEATURE_INDEX_1
+#define index_arch_POPCNT_Usable FEATURE_INDEX_1
+#define index_arch_AES_Usable FEATURE_INDEX_1
+#define index_arch_XSAVE_Usable FEATURE_INDEX_1
+#define index_arch_OSXSAVE_Usable FEATURE_INDEX_1
+#define index_arch_F16C_Usable FEATURE_INDEX_1
+#define index_arch_RDRAND_Usable FEATURE_INDEX_1
+#define index_arch_FPU_Usable FEATURE_INDEX_1
+#define index_arch_TSC_Usable FEATURE_INDEX_1
+#define index_arch_MSR_Usable FEATURE_INDEX_1
+#define index_arch_CX8_Usable FEATURE_INDEX_1
+#define index_arch_SEP_Usable FEATURE_INDEX_1
+#define index_arch_CMOV_Usable FEATURE_INDEX_1
+#define index_arch_CLFSH_Usable FEATURE_INDEX_1
+#define index_arch_MMX_Usable FEATURE_INDEX_1
+#define index_arch_FXSR_Usable FEATURE_INDEX_1
+#define index_arch_SSE_Usable FEATURE_INDEX_1
+#define index_arch_SSE2_Usable FEATURE_INDEX_1
+#define index_arch_FSGSBASE_Usable FEATURE_INDEX_1
+#define index_arch_BMI1_Usable FEATURE_INDEX_1
+#define index_arch_HLE_Usable FEATURE_INDEX_1
+#define index_arch_BMI2_Usable FEATURE_INDEX_1
+#define index_arch_ERMS_Usable FEATURE_INDEX_1
+#define index_arch_RTM_Usable FEATURE_INDEX_1
+#define index_arch_RDSEED_Usable FEATURE_INDEX_1
+#define index_arch_ADX_Usable FEATURE_INDEX_1
+#define index_arch_CLFLUSHOPT_Usable FEATURE_INDEX_1
+#define index_arch_CLWB_Usable FEATURE_INDEX_1
+#define index_arch_SHA_Usable FEATURE_INDEX_1
+#define index_arch_PREFETCHWT1_Usable FEATURE_INDEX_1
+#define index_arch_GFNI_Usable FEATURE_INDEX_1
+#define index_arch_RDPID_Usable FEATURE_INDEX_1
+#define index_arch_CLDEMOTE_Usable FEATURE_INDEX_1
+#define index_arch_MOVDIRI_Usable FEATURE_INDEX_1
+#define index_arch_MOVDIR64B_Usable FEATURE_INDEX_1
+#define index_arch_FSRM_Usable FEATURE_INDEX_1
+#define index_arch_LAHF64_SAHF64_Usable FEATURE_INDEX_1
+#define index_arch_LZCNT_Usable FEATURE_INDEX_1
+#define index_arch_SSE4A_Usable FEATURE_INDEX_1
+#define index_arch_PREFETCHW_Usable FEATURE_INDEX_1
+#define index_arch_TBM_Usable FEATURE_INDEX_1
+#define index_arch_SYSCALL_SYSRET_Usable FEATURE_INDEX_1
+#define index_arch_RDTSCP_Usable FEATURE_INDEX_1
+
+/* COMMON_CPUID_INDEX_1. */
+
+/* ECX. */
+#define need_arch_feature_SSE3 0
+#define need_arch_feature_PCLMULQDQ 0
+#define need_arch_feature_SSSE3 0
+#define need_arch_feature_FMA 1
+#define need_arch_feature_CMPXCHG16B 0
+#define need_arch_feature_SSE4_1 0
+#define need_arch_feature_SSE4_2 0
+#define need_arch_feature_MOVBE 0
+#define need_arch_feature_POPCNT 0
+#define need_arch_feature_AES 0
+#define need_arch_feature_XSAVE 0
+#define need_arch_feature_OSXSAVE 0
+#define need_arch_feature_AVX 1
+#define need_arch_feature_F16C 0
+#define need_arch_feature_RDRAND 0
+
+/* EDX. */
+#define need_arch_feature_FPU 0
+#define need_arch_feature_TSC 0
+#define need_arch_feature_MSR 0
+#define need_arch_feature_CX8 0
+#define need_arch_feature_SEP 0
+#define need_arch_feature_CMOV 0
+#define need_arch_feature_CLFSH 0
+#define need_arch_feature_MMX 0
+#define need_arch_feature_FXSR 0
+#define need_arch_feature_SSE 0
+#define need_arch_feature_SSE2 0
+
+/* COMMON_CPUID_INDEX_7. */
+
+/* EBX. */
+#define need_arch_feature_FSGSBASE 0
+#define need_arch_feature_BMI1 0
+#define need_arch_feature_HLE 0
+#define need_arch_feature_AVX2 1
+#define need_arch_feature_BMI2 0
+#define need_arch_feature_ERMS 0
+#define need_arch_feature_RTM 0
+#define need_arch_feature_AVX512F 1
+#define need_arch_feature_AVX512DQ 1
+#define need_arch_feature_RDSEED 0
+#define need_arch_feature_ADX 0
+#define need_arch_feature_AVX512_IFMA 1
+#define need_arch_feature_CLFLUSHOPT 0
+#define need_arch_feature_CLWB 0
+#define need_arch_feature_AVX512PF 1
+#define need_arch_feature_AVX512ER 1
+#define need_arch_feature_AVX512CD 1
+#define need_arch_feature_SHA 0
+#define need_arch_feature_AVX512BW 1
+#define need_arch_feature_AVX512VL 1
+
+/* ECX. */
+#define need_arch_feature_PREFETCHWT1 0
+#define need_arch_feature_AVX512_VBMI 1
+#define need_arch_feature_AVX512_VBMI2 1
+#define need_arch_feature_GFNI 0
+#define need_arch_feature_VAES 1
+#define need_arch_feature_VPCLMULQDQ 1
+#define need_arch_feature_AVX512_VNNI 1
+#define need_arch_feature_AVX512_BITALG 1
+#define need_arch_feature_AVX512_VPOPCNTDQ 1
+#define need_arch_feature_RDPID 0
+#define need_arch_feature_CLDEMOTE 0
+#define need_arch_feature_MOVDIRI 0
+#define need_arch_feature_MOVDIR64B 0
+
+/* EDX. */
+#define need_arch_feature_AVX512_4VNNIW 1
+#define need_arch_feature_AVX512_4FMAPS 1
+#define need_arch_feature_FSRM 0
+
+/* COMMON_CPUID_INDEX_80000001. */
+
+/* ECX. */
+#define need_arch_feature_LAHF64_SAHF64 0
+#define need_arch_feature_LZCNT 0
+#define need_arch_feature_SSE4A 0
+#define need_arch_feature_PREFETCHW 0
+#define need_arch_feature_XOP 1
+#define need_arch_feature_FMA4 1
+#define need_arch_feature_TBM 0
+#define need_arch_feature_SYSCALL_SYSRET 0
+#define need_arch_feature_RDTSCP 0
+
+/* CPU features. */
+
+/* COMMON_CPUID_INDEX_1. */
+
+/* ECX. */
+#define bit_cpu_SSE3 (1u << 0)
+#define bit_cpu_PCLMULQDQ (1u << 1)
+#define bit_cpu_DTES64 (1u << 2)
+#define bit_cpu_MONITOR (1u << 3)
+#define bit_cpu_DS_CPL (1u << 4)
+#define bit_cpu_VMX (1u << 5)
+#define bit_cpu_SMX (1u << 6)
+#define bit_cpu_EST (1u << 7)
+#define bit_cpu_TM2 (1u << 8)
+#define bit_cpu_SSSE3 (1u << 9)
+#define bit_cpu_CNXT_ID (1u << 10)
+#define bit_cpu_SDBG (1u << 11)
+#define bit_cpu_FMA (1u << 12)
+#define bit_cpu_CMPXCHG16B (1u << 13)
+#define bit_cpu_XTPRUPDCTRL (1u << 14)
+#define bit_cpu_PDCM (1u << 15)
+#define bit_cpu_PCID (1u << 17)
+#define bit_cpu_DCA (1u << 18)
+#define bit_cpu_SSE4_1 (1u << 19)
+#define bit_cpu_SSE4_2 (1u << 20)
+#define bit_cpu_X2APIC (1u << 21)
+#define bit_cpu_MOVBE (1u << 22)
+#define bit_cpu_POPCNT (1u << 23)
+#define bit_cpu_TSC_DEADLINE (1u << 24)
+#define bit_cpu_AES (1u << 25)
+#define bit_cpu_XSAVE (1u << 26)
+#define bit_cpu_OSXSAVE (1u << 27)
+#define bit_cpu_AVX (1u << 28)
+#define bit_cpu_F16C (1u << 29)
+#define bit_cpu_RDRAND (1u << 30)
+
+/* EDX. */
+#define bit_cpu_FPU (1u << 0)
+#define bit_cpu_VME (1u << 1)
+#define bit_cpu_DE (1u << 2)
+#define bit_cpu_PSE (1u << 3)
+#define bit_cpu_TSC (1u << 4)
+#define bit_cpu_MSR (1u << 5)
+#define bit_cpu_PAE (1u << 6)
+#define bit_cpu_MCE (1u << 7)
+#define bit_cpu_CX8 (1u << 8)
+#define bit_cpu_APIC (1u << 9)
+#define bit_cpu_SEP (1u << 11)
+#define bit_cpu_MTRR (1u << 12)
+#define bit_cpu_PGE (1u << 13)
+#define bit_cpu_MCA (1u << 14)
+#define bit_cpu_CMOV (1u << 15)
+#define bit_cpu_PAT (1u << 16)
+#define bit_cpu_PSE_36 (1u << 17)
+#define bit_cpu_PSN (1u << 18)
+#define bit_cpu_CLFSH (1u << 20)
+#define bit_cpu_DS (1u << 21)
+#define bit_cpu_ACPI (1u << 22)
+#define bit_cpu_MMX (1u << 23)
+#define bit_cpu_FXSR (1u << 24)
+#define bit_cpu_SSE (1u << 25)
+#define bit_cpu_SSE2 (1u << 26)
+#define bit_cpu_SS (1u << 27)
+#define bit_cpu_HTT (1u << 28)
+#define bit_cpu_TM (1u << 29)
+#define bit_cpu_PBE (1u << 31)
+
+/* COMMON_CPUID_INDEX_7. */
+
+/* EBX. */
+#define bit_cpu_FSGSBASE (1u << 0)
+#define bit_cpu_TSC_ADJUST (1u << 1)
+#define bit_cpu_SGX (1u << 2)
+#define bit_cpu_BMI1 (1u << 3)
+#define bit_cpu_HLE (1u << 4)
+#define bit_cpu_AVX2 (1u << 5)
+#define bit_cpu_SMEP (1u << 7)
+#define bit_cpu_BMI2 (1u << 8)
+#define bit_cpu_ERMS (1u << 9)
+#define bit_cpu_INVPCID (1u << 10)
+#define bit_cpu_RTM (1u << 11)
+#define bit_cpu_PQM (1u << 12)
+#define bit_cpu_MPX (1u << 14)
+#define bit_cpu_PQE (1u << 15)
+#define bit_cpu_AVX512F (1u << 16)
+#define bit_cpu_AVX512DQ (1u << 17)
+#define bit_cpu_RDSEED (1u << 18)
+#define bit_cpu_ADX (1u << 19)
+#define bit_cpu_SMAP (1u << 20)
+#define bit_cpu_AVX512_IFMA (1u << 21)
+#define bit_cpu_CLFLUSHOPT (1u << 22)
+#define bit_cpu_CLWB (1u << 24)
+#define bit_cpu_TRACE (1u << 25)
+#define bit_cpu_AVX512PF (1u << 26)
+#define bit_cpu_AVX512ER (1u << 27)
+#define bit_cpu_AVX512CD (1u << 28)
+#define bit_cpu_SHA (1u << 29)
+#define bit_cpu_AVX512BW (1u << 30)
+#define bit_cpu_AVX512VL (1u << 31)
+
+/* ECX. */
+#define bit_cpu_PREFETCHWT1 (1u << 0)
+#define bit_cpu_AVX512_VBMI (1u << 1)
+#define bit_cpu_UMIP (1u << 2)
+#define bit_cpu_PKU (1u << 3)
+#define bit_cpu_OSPKE (1u << 4)
+#define bit_cpu_WAITPKG (1u << 5)
+#define bit_cpu_SHSTK (1u << 7)
+#define bit_cpu_AVX512_VBMI2 (1u << 6)
+#define bit_cpu_GFNI (1u << 8)
+#define bit_cpu_VAES (1u << 9)
+#define bit_cpu_VPCLMULQDQ (1u << 10)
+#define bit_cpu_AVX512_VNNI (1u << 11)
+#define bit_cpu_AVX512_BITALG (1u << 12)
+#define bit_cpu_AVX512_VPOPCNTDQ (1u << 14)
+#define bit_cpu_RDPID (1u << 22)
+#define bit_cpu_CLDEMOTE (1u << 25)
+#define bit_cpu_MOVDIRI (1u << 27)
+#define bit_cpu_MOVDIR64B (1u << 28)
+#define bit_cpu_SGX_LC (1u << 30)
+
+/* EDX. */
+#define bit_cpu_AVX512_4VNNIW (1u << 2)
+#define bit_cpu_AVX512_4FMAPS (1u << 3)
+#define bit_cpu_FSRM (1u << 4)
+#define bit_cpu_PCONFIG (1u << 18)
+#define bit_cpu_IBT (1u << 20)
+
+/* COMMON_CPUID_INDEX_80000001. */
+
+/* ECX. */
+#define bit_cpu_LAHF64_SAHF64 (1u << 0)
+#define bit_cpu_SVM (1u << 2)
+#define bit_cpu_LZCNT (1u << 5)
+#define bit_cpu_SSE4A (1u << 6)
+#define bit_cpu_PREFETCHW (1u << 8)
+#define bit_cpu_XOP (1u << 11)
+#define bit_cpu_LWP (1u << 15)
+#define bit_cpu_FMA4 (1u << 16)
+#define bit_cpu_TBM (1u << 21)
+
+/* EDX. */
+#define bit_cpu_SYSCALL_SYSRET (1u << 11)
+#define bit_cpu_NX (1u << 20)
+#define bit_cpu_PAGE1GB (1u << 26)
+#define bit_cpu_RDTSCP (1u << 27)
+#define bit_cpu_LM (1u << 29)
+
+/* COMMON_CPUID_INDEX_1. */
+
+/* ECX. */
+#define index_cpu_SSE3 COMMON_CPUID_INDEX_1
+#define index_cpu_PCLMULQDQ COMMON_CPUID_INDEX_1
+#define index_cpu_DTES64 COMMON_CPUID_INDEX_1
+#define index_cpu_MONITOR COMMON_CPUID_INDEX_1
+#define index_cpu_DS_CPL COMMON_CPUID_INDEX_1
+#define index_cpu_VMX COMMON_CPUID_INDEX_1
+#define index_cpu_SMX COMMON_CPUID_INDEX_1
+#define index_cpu_EST COMMON_CPUID_INDEX_1
+#define index_cpu_TM2 COMMON_CPUID_INDEX_1
+#define index_cpu_SSSE3 COMMON_CPUID_INDEX_1
+#define index_cpu_CNXT_ID COMMON_CPUID_INDEX_1
+#define index_cpu_SDBG COMMON_CPUID_INDEX_1
+#define index_cpu_FMA COMMON_CPUID_INDEX_1
+#define index_cpu_CMPXCHG16B COMMON_CPUID_INDEX_1
+#define index_cpu_XTPRUPDCTRL COMMON_CPUID_INDEX_1
+#define index_cpu_PDCM COMMON_CPUID_INDEX_1
+#define index_cpu_PCID COMMON_CPUID_INDEX_1
+#define index_cpu_DCA COMMON_CPUID_INDEX_1
+#define index_cpu_SSE4_1 COMMON_CPUID_INDEX_1
+#define index_cpu_SSE4_2 COMMON_CPUID_INDEX_1
+#define index_cpu_X2APIC COMMON_CPUID_INDEX_1
+#define index_cpu_MOVBE COMMON_CPUID_INDEX_1
+#define index_cpu_POPCNT COMMON_CPUID_INDEX_1
+#define index_cpu_TSC_DEADLINE COMMON_CPUID_INDEX_1
+#define index_cpu_AES COMMON_CPUID_INDEX_1
+#define index_cpu_XSAVE COMMON_CPUID_INDEX_1
+#define index_cpu_OSXSAVE COMMON_CPUID_INDEX_1
+#define index_cpu_AVX COMMON_CPUID_INDEX_1
+#define index_cpu_F16C COMMON_CPUID_INDEX_1
+#define index_cpu_RDRAND COMMON_CPUID_INDEX_1
+
+/* ECX. */
+#define index_cpu_FPU COMMON_CPUID_INDEX_1
+#define index_cpu_VME COMMON_CPUID_INDEX_1
+#define index_cpu_DE COMMON_CPUID_INDEX_1
+#define index_cpu_PSE COMMON_CPUID_INDEX_1
+#define index_cpu_TSC COMMON_CPUID_INDEX_1
+#define index_cpu_MSR COMMON_CPUID_INDEX_1
+#define index_cpu_PAE COMMON_CPUID_INDEX_1
+#define index_cpu_MCE COMMON_CPUID_INDEX_1
+#define index_cpu_CX8 COMMON_CPUID_INDEX_1
+#define index_cpu_APIC COMMON_CPUID_INDEX_1
+#define index_cpu_SEP COMMON_CPUID_INDEX_1
+#define index_cpu_MTRR COMMON_CPUID_INDEX_1
+#define index_cpu_PGE COMMON_CPUID_INDEX_1
+#define index_cpu_MCA COMMON_CPUID_INDEX_1
+#define index_cpu_CMOV COMMON_CPUID_INDEX_1
+#define index_cpu_PAT COMMON_CPUID_INDEX_1
+#define index_cpu_PSE_36 COMMON_CPUID_INDEX_1
+#define index_cpu_PSN COMMON_CPUID_INDEX_1
+#define index_cpu_CLFSH COMMON_CPUID_INDEX_1
+#define index_cpu_DS COMMON_CPUID_INDEX_1
+#define index_cpu_ACPI COMMON_CPUID_INDEX_1
+#define index_cpu_MMX COMMON_CPUID_INDEX_1
+#define index_cpu_FXSR COMMON_CPUID_INDEX_1
+#define index_cpu_SSE COMMON_CPUID_INDEX_1
+#define index_cpu_SSE2 COMMON_CPUID_INDEX_1
+#define index_cpu_SS COMMON_CPUID_INDEX_1
+#define index_cpu_HTT COMMON_CPUID_INDEX_1
+#define index_cpu_TM COMMON_CPUID_INDEX_1
+#define index_cpu_PBE COMMON_CPUID_INDEX_1
+
+/* COMMON_CPUID_INDEX_7. */
+
+/* EBX. */
+#define index_cpu_FSGSBASE COMMON_CPUID_INDEX_7
+#define index_cpu_TSC_ADJUST COMMON_CPUID_INDEX_7
+#define index_cpu_SGX COMMON_CPUID_INDEX_7
+#define index_cpu_BMI1 COMMON_CPUID_INDEX_7
+#define index_cpu_HLE COMMON_CPUID_INDEX_7
+#define index_cpu_AVX2 COMMON_CPUID_INDEX_7
+#define index_cpu_SMEP COMMON_CPUID_INDEX_7
+#define index_cpu_BMI2 COMMON_CPUID_INDEX_7
+#define index_cpu_ERMS COMMON_CPUID_INDEX_7
+#define index_cpu_INVPCID COMMON_CPUID_INDEX_7
+#define index_cpu_RTM COMMON_CPUID_INDEX_7
+#define index_cpu_PQM COMMON_CPUID_INDEX_7
+#define index_cpu_MPX COMMON_CPUID_INDEX_7
+#define index_cpu_PQE COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512F COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512DQ COMMON_CPUID_INDEX_7
+#define index_cpu_RDSEED COMMON_CPUID_INDEX_7
+#define index_cpu_ADX COMMON_CPUID_INDEX_7
+#define index_cpu_SMAP COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512_IFMA COMMON_CPUID_INDEX_7
+#define index_cpu_CLFLUSHOPT COMMON_CPUID_INDEX_7
+#define index_cpu_CLWB COMMON_CPUID_INDEX_7
+#define index_cpu_TRACE COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512PF COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512ER COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512CD COMMON_CPUID_INDEX_7
+#define index_cpu_SHA COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512BW COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512VL COMMON_CPUID_INDEX_7
+
+/* ECX. */
+#define index_cpu_PREFETCHWT1 COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512_VBMI COMMON_CPUID_INDEX_7
+#define index_cpu_UMIP COMMON_CPUID_INDEX_7
+#define index_cpu_PKU COMMON_CPUID_INDEX_7
+#define index_cpu_OSPKE COMMON_CPUID_INDEX_7
+#define index_cpu_WAITPKG COMMON_CPUID_INDEX_7
+#define index_cpu_SHSTK COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512_VBMI2 COMMON_CPUID_INDEX_7
+#define index_cpu_GFNI COMMON_CPUID_INDEX_7
+#define index_cpu_VAES COMMON_CPUID_INDEX_7
+#define index_cpu_VPCLMULQDQ COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512_VNNI COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512_BITALG COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512_VPOPCNTDQ COMMON_CPUID_INDEX_7
+#define index_cpu_RDPID COMMON_CPUID_INDEX_7
+#define index_cpu_CLDEMOTE COMMON_CPUID_INDEX_7
+#define index_cpu_MOVDIRI COMMON_CPUID_INDEX_7
+#define index_cpu_MOVDIR64B COMMON_CPUID_INDEX_7
+#define index_cpu_SGX_LC COMMON_CPUID_INDEX_7
+
+/* EDX. */
+#define index_cpu_AVX512_4VNNIW COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512_4FMAPS COMMON_CPUID_INDEX_7
+#define index_cpu_FSRM COMMON_CPUID_INDEX_7
+#define index_cpu_PCONFIG COMMON_CPUID_INDEX_7
+#define index_cpu_IBT COMMON_CPUID_INDEX_7
+
+/* COMMON_CPUID_INDEX_80000001. */
+
+/* ECX. */
+#define index_cpu_LAHF64_SAHF64 COMMON_CPUID_INDEX_80000001
+#define index_cpu_SVM COMMON_CPUID_INDEX_80000001
+#define index_cpu_LZCNT COMMON_CPUID_INDEX_80000001
+#define index_cpu_SSE4A COMMON_CPUID_INDEX_80000001
+#define index_cpu_PREFETCHW COMMON_CPUID_INDEX_80000001
+#define index_cpu_XOP COMMON_CPUID_INDEX_80000001
+#define index_cpu_LWP COMMON_CPUID_INDEX_80000001
+#define index_cpu_FMA4 COMMON_CPUID_INDEX_80000001
+#define index_cpu_TBM COMMON_CPUID_INDEX_80000001
+
+/* EDX. */
+#define index_cpu_SYSCALL_SYSRET COMMON_CPUID_INDEX_80000001
+#define index_cpu_NX COMMON_CPUID_INDEX_80000001
+#define index_cpu_PAGE1GB COMMON_CPUID_INDEX_80000001
+#define index_cpu_RDTSCP COMMON_CPUID_INDEX_80000001
+#define index_cpu_LM COMMON_CPUID_INDEX_80000001
+
+/* COMMON_CPUID_INDEX_1. */
+
+/* ECX. */
+#define reg_SSE3 ecx
+#define reg_PCLMULQDQ ecx
+#define reg_DTES64 ecx
+#define reg_MONITOR ecx
+#define reg_DS_CPL ecx
+#define reg_VMX ecx
+#define reg_SMX ecx
+#define reg_EST ecx
+#define reg_TM2 ecx
+#define reg_SSSE3 ecx
+#define reg_CNXT_ID ecx
+#define reg_SDBG ecx
+#define reg_FMA ecx
+#define reg_CMPXCHG16B ecx
+#define reg_XTPRUPDCTRL ecx
+#define reg_PDCM ecx
+#define reg_PCID ecx
+#define reg_DCA ecx
+#define reg_SSE4_1 ecx
+#define reg_SSE4_2 ecx
+#define reg_X2APIC ecx
+#define reg_MOVBE ecx
+#define reg_POPCNT ecx
+#define reg_TSC_DEADLINE ecx
+#define reg_AES ecx
+#define reg_XSAVE ecx
+#define reg_OSXSAVE ecx
+#define reg_AVX ecx
+#define reg_F16C ecx
+#define reg_RDRAND ecx
+
+/* EDX. */
+#define reg_FPU edx
+#define reg_VME edx
+#define reg_DE edx
+#define reg_PSE edx
+#define reg_TSC edx
+#define reg_MSR edx
+#define reg_PAE edx
+#define reg_MCE edx
+#define reg_CX8 edx
+#define reg_APIC edx
+#define reg_SEP edx
+#define reg_MTRR edx
+#define reg_PGE edx
+#define reg_MCA edx
+#define reg_CMOV edx
+#define reg_PAT edx
+#define reg_PSE_36 edx
+#define reg_PSN edx
+#define reg_CLFSH edx
+#define reg_DS edx
+#define reg_ACPI edx
+#define reg_MMX edx
+#define reg_FXSR edx
+#define reg_SSE edx
+#define reg_SSE2 edx
+#define reg_SS edx
+#define reg_HTT edx
+#define reg_TM edx
+#define reg_PBE edx
+
+/* COMMON_CPUID_INDEX_7. */
+
+/* EBX. */
+#define reg_FSGSBASE ebx
+#define reg_TSC_ADJUST ebx
+#define reg_SGX ebx
+#define reg_BMI1 ebx
+#define reg_HLE ebx
+#define reg_BMI2 ebx
+#define reg_AVX2 ebx
+#define reg_SMEP ebx
+#define reg_ERMS ebx
+#define reg_INVPCID ebx
+#define reg_RTM ebx
+#define reg_PQM ebx
+#define reg_MPX ebx
+#define reg_PQE ebx
+#define reg_AVX512F ebx
+#define reg_AVX512DQ ebx
+#define reg_RDSEED ebx
+#define reg_ADX ebx
+#define reg_SMAP ebx
+#define reg_AVX512_IFMA ebx
+#define reg_CLFLUSHOPT ebx
+#define reg_CLWB ebx
+#define reg_TRACE ebx
+#define reg_AVX512PF ebx
+#define reg_AVX512ER ebx
+#define reg_AVX512CD ebx
+#define reg_SHA ebx
+#define reg_AVX512BW ebx
+#define reg_AVX512VL ebx
+
+/* ECX. */
+#define reg_PREFETCHWT1 ecx
+#define reg_AVX512_VBMI ecx
+#define reg_UMIP ecx
+#define reg_PKU ecx
+#define reg_OSPKE ecx
+#define reg_WAITPKG ecx
+#define reg_SHSTK ecx
+#define reg_AVX512_VBMI2 ecx
+#define reg_GFNI ecx
+#define reg_VAES ecx
+#define reg_VPCLMULQDQ ecx
+#define reg_AVX512_VNNI ecx
+#define reg_AVX512_BITALG ecx
+#define reg_AVX512_VPOPCNTDQ ecx
+#define reg_RDPID ecx
+#define reg_CLDEMOTE ecx
+#define reg_MOVDIRI ecx
+#define reg_MOVDIR64B ecx
+#define reg_SGX_LC ecx
+
+/* EDX. */
+#define reg_AVX512_4VNNIW edx
+#define reg_AVX512_4FMAPS edx
+#define reg_FSRM edx
+#define reg_PCONFIG edx
+#define reg_IBT edx
+
+/* COMMON_CPUID_INDEX_80000001. */
+
+/* ECX. */
+#define reg_LAHF64_SAHF64 ecx
+#define reg_SVM ecx
+#define reg_LZCNT ecx
+#define reg_SSE4A ecx
+#define reg_PREFETCHW ecx
+#define reg_XOP ecx
+#define reg_LWP ecx
+#define reg_FMA4 ecx
+#define reg_TBM ecx
+
+/* EDX. */
+#define reg_SYSCALL_SYSRET edx
+#define reg_NX edx
+#define reg_PAGE1GB edx
+#define reg_RDTSCP edx
+#define reg_LM edx
+
+__END_DECLS
+
+#endif /* _SYS_PLATFORM_X86_H */
@@ -17,15 +17,36 @@
<http://www.gnu.org/licenses/>. */
#include <stdlib.h>
+#include <stdio.h>
#include <cpu-features.h>
+#include <support/check.h>
+
+static const char * const cpu_kinds[] =
+{
+ "Unknown",
+ "Intel",
+ "AMD",
+ "Other",
+};
static int
do_test (void)
{
- if (__get_cpu_features ()->kind == arch_kind_unknown)
- abort ();
+ enum cpu_features_kind kind = __get_cpu_features ()->kind;
+
+ switch (kind)
+ {
+ case arch_kind_intel:
+ case arch_kind_amd:
+ case arch_kind_other:
+ printf ("Vendor: %s\n", cpu_kinds[kind]);
+ break;
+
+ default:
+ abort ();
+ }
+
return 0;
}
-#define TEST_FUNCTION do_test ()
-#include "../../test-skeleton.c"
+#include <support/test-driver.c>
new file mode 100644
@@ -0,0 +1 @@
+#include "tst-x86-platform-1.c"
new file mode 100644
@@ -0,0 +1,116 @@
+/* Test case for x86 <sys/platform/x86.h>.
+ Copyright (C) 2018 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <sys/platform/x86.h>
+#include <support/check.h>
+
+#define CHECK_CPU_FEATURE_USABLE(name) \
+ { \
+ if (CPU_FEATURE_USABLE(name)) \
+ printf (" " #name "\n"); \
+ }
+
+
+#ifdef DO_TEST_FUNCTION
+int
+DO_TEST_FUNCTION (void)
+#else
+static int
+do_test (void)
+#endif
+{
+ printf ("Usable CPU features:\n");
+ CHECK_CPU_FEATURE_USABLE (SSE3);
+ CHECK_CPU_FEATURE_USABLE (PCLMULQDQ);
+ CHECK_CPU_FEATURE_USABLE (SSSE3);
+ CHECK_CPU_FEATURE_USABLE (FMA);
+ CHECK_CPU_FEATURE_USABLE (CMPXCHG16B);
+ CHECK_CPU_FEATURE_USABLE (SSE4_1);
+ CHECK_CPU_FEATURE_USABLE (SSE4_2);
+ CHECK_CPU_FEATURE_USABLE (MOVBE);
+ CHECK_CPU_FEATURE_USABLE (POPCNT);
+ CHECK_CPU_FEATURE_USABLE (AES);
+ CHECK_CPU_FEATURE_USABLE (XSAVE);
+ CHECK_CPU_FEATURE_USABLE (OSXSAVE);
+ CHECK_CPU_FEATURE_USABLE (AVX);
+ CHECK_CPU_FEATURE_USABLE (F16C);
+ CHECK_CPU_FEATURE_USABLE (RDRAND);
+ CHECK_CPU_FEATURE_USABLE (FPU);
+ CHECK_CPU_FEATURE_USABLE (TSC);
+ CHECK_CPU_FEATURE_USABLE (MSR);
+ CHECK_CPU_FEATURE_USABLE (CX8);
+ CHECK_CPU_FEATURE_USABLE (SEP);
+ CHECK_CPU_FEATURE_USABLE (CMOV);
+ CHECK_CPU_FEATURE_USABLE (CLFSH);
+ CHECK_CPU_FEATURE_USABLE (MMX);
+ CHECK_CPU_FEATURE_USABLE (FXSR);
+ CHECK_CPU_FEATURE_USABLE (SSE);
+ CHECK_CPU_FEATURE_USABLE (SSE2);
+ CHECK_CPU_FEATURE_USABLE (FSGSBASE);
+ CHECK_CPU_FEATURE_USABLE (BMI1);
+ CHECK_CPU_FEATURE_USABLE (HLE);
+ CHECK_CPU_FEATURE_USABLE (AVX2);
+ CHECK_CPU_FEATURE_USABLE (BMI2);
+ CHECK_CPU_FEATURE_USABLE (ERMS);
+ CHECK_CPU_FEATURE_USABLE (AVX512F);
+ CHECK_CPU_FEATURE_USABLE (AVX512DQ);
+ CHECK_CPU_FEATURE_USABLE (RDSEED);
+ CHECK_CPU_FEATURE_USABLE (ADX);
+ CHECK_CPU_FEATURE_USABLE (AVX512_IFMA);
+ CHECK_CPU_FEATURE_USABLE (CLFLUSHOPT);
+ CHECK_CPU_FEATURE_USABLE (CLWB);
+ CHECK_CPU_FEATURE_USABLE (AVX512PF);
+ CHECK_CPU_FEATURE_USABLE (AVX512ER);
+ CHECK_CPU_FEATURE_USABLE (AVX512CD);
+ CHECK_CPU_FEATURE_USABLE (SHA);
+ CHECK_CPU_FEATURE_USABLE (AVX512BW);
+ CHECK_CPU_FEATURE_USABLE (AVX512VL);
+ CHECK_CPU_FEATURE_USABLE (PREFETCHWT1);
+ CHECK_CPU_FEATURE_USABLE (AVX512_VBMI);
+ CHECK_CPU_FEATURE_USABLE (AVX512_VBMI2);
+ CHECK_CPU_FEATURE_USABLE (GFNI);
+ CHECK_CPU_FEATURE_USABLE (VAES);
+ CHECK_CPU_FEATURE_USABLE (VPCLMULQDQ);
+ CHECK_CPU_FEATURE_USABLE (AVX512_VNNI);
+ CHECK_CPU_FEATURE_USABLE (AVX512_BITALG);
+ CHECK_CPU_FEATURE_USABLE (AVX512_VPOPCNTDQ);
+ CHECK_CPU_FEATURE_USABLE (RDPID);
+ CHECK_CPU_FEATURE_USABLE (CLDEMOTE);
+ CHECK_CPU_FEATURE_USABLE (MOVDIRI);
+ CHECK_CPU_FEATURE_USABLE (MOVDIR64B);
+ CHECK_CPU_FEATURE_USABLE (AVX512_4VNNIW);
+ CHECK_CPU_FEATURE_USABLE (AVX512_4FMAPS);
+ CHECK_CPU_FEATURE_USABLE (FSRM);
+ CHECK_CPU_FEATURE_USABLE (LAHF64_SAHF64);
+ CHECK_CPU_FEATURE_USABLE (LZCNT);
+ CHECK_CPU_FEATURE_USABLE (SSE4A);
+ CHECK_CPU_FEATURE_USABLE (PREFETCHW);
+ CHECK_CPU_FEATURE_USABLE (XOP);
+ CHECK_CPU_FEATURE_USABLE (FMA4);
+ CHECK_CPU_FEATURE_USABLE (TBM);
+ CHECK_CPU_FEATURE_USABLE (SYSCALL_SYSRET);
+ CHECK_CPU_FEATURE_USABLE (RDTSCP);
+
+ return 0;
+}
+
+#ifndef DO_TEST_FUNCTION
+#include <support/test-driver.c>
+#endif
new file mode 100644
@@ -0,0 +1,27 @@
+/* Test case for x86 <sys/platform/x86.h>.
+ Copyright (C) 2018 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+extern int do_test_function (void);
+
+static int
+do_test (void)
+{
+ return do_test_function ();
+}
+
+#include <support/test-driver.c>
new file mode 100644
@@ -0,0 +1,27 @@
+/* Test case for x86 <sys/platform/x86.h>.
+ Copyright (C) 2018 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+extern int do_test_function (void);
+
+static int
+do_test (void)
+{
+ return do_test_function ();
+}
+
+#include <support/test-driver.c>
new file mode 100644
@@ -0,0 +1,2 @@
+#define DO_TEST_FUNCTION do_test_function
+#include "tst-x86-platform-1.c"
new file mode 100644
@@ -0,0 +1,2 @@
+#define DO_TEST_FUNCTION do_test_function
+#include "tst-x86-platform-1.c"
@@ -33,4 +33,4 @@
#undef __sched_cpucount
libc_ifunc (__sched_cpucount,
- HAS_CPU_FEATURE (POPCOUNT) ? popcount_cpucount : generic_cpucount);
+ HAS_CPU_FEATURE (POPCNT) ? popcount_cpucount : generic_cpucount);
@@ -85,8 +85,8 @@ do_test (int argc, char **argv)
, "HAS_CPU_FEATURE (SSE4_1)");
fails += check_proc ("ssse3", HAS_CPU_FEATURE (SSSE3),
"HAS_CPU_FEATURE (SSSE3)");
- fails += check_proc ("popcnt", HAS_CPU_FEATURE (POPCOUNT),
- "HAS_CPU_FEATURE (POPCOUNT)");
+ fails += check_proc ("popcnt", HAS_CPU_FEATURE (POPCNT),
+ "HAS_CPU_FEATURE (POPCNT)");
printf ("%d differences between /proc/cpuinfo and glibc code.\n", fails);
--
2.17.2