x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
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dj/TryBot-apply_patch |
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Patch applied to master at the time it was sent
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dj/TryBot-32bit |
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Build for i686
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Commit Message
From
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated,
which is set to indicate to updated software that the loaded microcode is
forcing RTM abort.
1. Add RTM_ALWAYS_ABORT to CPUID features.
2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.
3. Check RTM feature, instead of usability, against /proc/cpuinfo.
This fixes BZ #28033.
---
manual/platform.texi | 3 +++
sysdeps/x86/bits/platform/x86.h | 2 +-
sysdeps/x86/cpu-features.c | 4 +++-
sysdeps/x86/include/cpu-features.h | 6 +++---
sysdeps/x86/tst-cpu-features-supports.c | 2 +-
sysdeps/x86/tst-get-cpu-features.c | 1 +
6 files changed, 12 insertions(+), 6 deletions(-)
Comments
* H. J. Lu via Libc-alpha:
> From
>
> https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
>
> A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated,
> which is set to indicate to updated software that the loaded microcode is
> forcing RTM abort.
>
> 1. Add RTM_ALWAYS_ABORT to CPUID features.
> 2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.
> 3. Check RTM feature, instead of usability, against /proc/cpuinfo.
Maybe not that this fixes the string/tst-memchr-rtm etc. test cases
after a microcde update?
> diff --git a/manual/platform.texi b/manual/platform.texi
> index 4cd029cfad..8ec7f385e9 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -525,6 +525,9 @@ capability.
> @item
> @code{RTM} -- RTM instruction extensions.
>
> +@item
> +@code{RTM_ALWAYS_ABORT} -- Abort all transactions.
I think this means “Transactions always abort, making RTM unusable.”
(with unusable in both senses, !CPU_FEATURE_USABLE, and not useful).
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index a1d8d11cc4..d9093f11ac 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -67,7 +67,6 @@ update_usable (struct cpu_features *cpu_features)
> CPU_FEATURE_SET_USABLE (cpu_features, HLE);
> CPU_FEATURE_SET_USABLE (cpu_features, BMI2);
> CPU_FEATURE_SET_USABLE (cpu_features, ERMS);
> - CPU_FEATURE_SET_USABLE (cpu_features, RTM);
> CPU_FEATURE_SET_USABLE (cpu_features, RDSEED);
> CPU_FEATURE_SET_USABLE (cpu_features, ADX);
> CPU_FEATURE_SET_USABLE (cpu_features, CLFLUSHOPT);
> @@ -97,6 +96,9 @@ update_usable (struct cpu_features *cpu_features)
> CPU_FEATURE_SET_USABLE (cpu_features, FSRCS);
> CPU_FEATURE_SET_USABLE (cpu_features, PTWRITE);
>
> + if (!CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT))
> + CPU_FEATURE_SET_USABLE (cpu_features, RTM);
> +
> #if CET_ENABLED
> CPU_FEATURE_SET_USABLE (cpu_features, IBT);
> CPU_FEATURE_SET_USABLE (cpu_features, SHSTK);
Is some change necessary to copy RTM_ALWAYS_ABORT to USABLE as well?
Any idea why the microcode update doesn't just clear the RPM bit in
CPUID? This is a bit awkward.
Thanks,
Florian
@@ -525,6 +525,9 @@ capability.
@item
@code{RTM} -- RTM instruction extensions.
+@item
+@code{RTM_ALWAYS_ABORT} -- Abort all transactions.
+
@item
@code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug.
@@ -211,7 +211,7 @@ enum
x86_cpu_AVX512_VP2INTERSECT = x86_cpu_index_7_edx + 8,
x86_cpu_INDEX_7_EDX_9 = x86_cpu_index_7_edx + 9,
x86_cpu_MD_CLEAR = x86_cpu_index_7_edx + 10,
- x86_cpu_INDEX_7_EDX_11 = x86_cpu_index_7_edx + 11,
+ x86_cpu_RTM_ALWAYS_ABORT = x86_cpu_index_7_edx + 11,
x86_cpu_INDEX_7_EDX_12 = x86_cpu_index_7_edx + 12,
x86_cpu_INDEX_7_EDX_13 = x86_cpu_index_7_edx + 13,
x86_cpu_SERIALIZE = x86_cpu_index_7_edx + 14,
@@ -67,7 +67,6 @@ update_usable (struct cpu_features *cpu_features)
CPU_FEATURE_SET_USABLE (cpu_features, HLE);
CPU_FEATURE_SET_USABLE (cpu_features, BMI2);
CPU_FEATURE_SET_USABLE (cpu_features, ERMS);
- CPU_FEATURE_SET_USABLE (cpu_features, RTM);
CPU_FEATURE_SET_USABLE (cpu_features, RDSEED);
CPU_FEATURE_SET_USABLE (cpu_features, ADX);
CPU_FEATURE_SET_USABLE (cpu_features, CLFLUSHOPT);
@@ -97,6 +96,9 @@ update_usable (struct cpu_features *cpu_features)
CPU_FEATURE_SET_USABLE (cpu_features, FSRCS);
CPU_FEATURE_SET_USABLE (cpu_features, PTWRITE);
+ if (!CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT))
+ CPU_FEATURE_SET_USABLE (cpu_features, RTM);
+
#if CET_ENABLED
CPU_FEATURE_SET_USABLE (cpu_features, IBT);
CPU_FEATURE_SET_USABLE (cpu_features, SHSTK);
@@ -229,7 +229,7 @@ enum
#define bit_cpu_AVX512_VP2INTERSECT (1u << 8)
#define bit_cpu_INDEX_7_EDX_9 (1u << 9)
#define bit_cpu_MD_CLEAR (1u << 10)
-#define bit_cpu_INDEX_7_EDX_11 (1u << 11)
+#define bit_cpu_RTM_ALWAYS_ABORT (1u << 11)
#define bit_cpu_INDEX_7_EDX_12 (1u << 12)
#define bit_cpu_INDEX_7_EDX_13 (1u << 13)
#define bit_cpu_SERIALIZE (1u << 14)
@@ -463,7 +463,7 @@ enum
#define index_cpu_AVX512_VP2INTERSECT CPUID_INDEX_7
#define index_cpu_INDEX_7_EDX_9 CPUID_INDEX_7
#define index_cpu_MD_CLEAR CPUID_INDEX_7
-#define index_cpu_INDEX_7_EDX_11 CPUID_INDEX_7
+#define index_cpu_RTM_ALWAYS_ABORT CPUID_INDEX_7
#define index_cpu_INDEX_7_EDX_12 CPUID_INDEX_7
#define index_cpu_INDEX_7_EDX_13 CPUID_INDEX_7
#define index_cpu_SERIALIZE CPUID_INDEX_7
@@ -697,7 +697,7 @@ enum
#define reg_AVX512_VP2INTERSECT edx
#define reg_INDEX_7_EDX_9 edx
#define reg_MD_CLEAR edx
-#define reg_INDEX_7_EDX_11 edx
+#define reg_RTM_ALWAYS_ABORT edx
#define reg_INDEX_7_EDX_12 edx
#define reg_INDEX_7_EDX_13 edx
#define reg_SERIALIZE edx
@@ -153,7 +153,7 @@ do_test (int argc, char **argv)
fails += CHECK_SUPPORTS (rdpid, RDPID);
fails += CHECK_SUPPORTS (rdrnd, RDRAND);
fails += CHECK_SUPPORTS (rdseed, RDSEED);
- fails += CHECK_SUPPORTS (rtm, RTM);
+ fails += CHECK_CPU_SUPPORTS (rtm, RTM);
fails += CHECK_SUPPORTS (serialize, SERIALIZE);
fails += CHECK_SUPPORTS (sha, SHA);
fails += CHECK_CPU_SUPPORTS (shstk, SHSTK);
@@ -158,6 +158,7 @@ do_test (void)
CHECK_CPU_FEATURE (UINTR);
CHECK_CPU_FEATURE (AVX512_VP2INTERSECT);
CHECK_CPU_FEATURE (MD_CLEAR);
+ CHECK_CPU_FEATURE (RTM_ALWAYS_ABORT);
CHECK_CPU_FEATURE (SERIALIZE);
CHECK_CPU_FEATURE (HYBRID);
CHECK_CPU_FEATURE (TSXLDTRK);